Can VSSA voltage be slightly lower than VSS? (STM32H7, ADC)

[TDJ]

I am wondering if VSSA voltage can be slightly lower than VSS? If so, what is the maximum allowed difference?
The reason why I ask is because I would like to measure voltage slightly (0.2-0.3V) below the common ground attached to VSS. I looked in several DSxxx documents (e.g. DS13195 and DS13196) but, to my surprise, I found no info/specification. I guess, a separate VSSA pin was made available on some MCUs so the voltage could slightly differ from VSS.

Could anyone advise?

[raptorhal2]

<VSSA voltage can be slightly lower than VSS? If so, what is the maximum allowed difference?>

Yes. The adc section in the data sheet will tell you tell you the maximum. When the input signal is at VSSA, the conversion result will be 4095 (12 bit) or 65535 (16 bit).

<I would like to measure voltage slightly (0.2-0.3V) below the common ground>

The ADC will not measure below common ground. An op-amp can be used to bias the signal to above ground. You can correct for that in the code after conversion.

<a separate VSSA pin was made available on some MCUs so the voltage could slightly differ from VSS.>

The separate pin is also for providing a relatively noise free reference to reduce adc conversion noise.

[TDJ]

> The adc section in the data sheet will tell you tell you the maximum

Well, it does not. At least not DS13195 or DS13196.

> The ADC will not measure below common ground.

Why not? According to specs ADC measures between VREF- and VREF+ while VREF- and VSSA are usually connected together hence if VSSA is below VSS, ADC should measure below VSS - and that is the point.

[AScha.3 · Accepted solution]

from ds H743 :  abs. max. rating :

+ working condition:

So possible : 50mV , without "guaranteed" working , just no damage.

+

For offset below gnd, just use a simple r-r divider.

Here -3 ...+3V possible. (at 3v3 V1 )

Or make R2 1k , then about -0.3 ...+3v input - without any risk. 🙂

[TDJ]

@AScha.3 Thanks, apparently in docs I was looking for VSSA, not VSSx. As you pointed out, applying input or previous stage offset with additional resistor(s) may be a practical solution, especially since VSS-VSSA < 50mV while I need 200-300mV offset. My solution requires many ADC channels so I was trying to avoid adding many additional resistors by applying the required offset at VSSA pin only.

[TDJ]

@AScha.3 There is one more factor which should be mention here for anyone who may come across this thread.
The above solution can be used to reliably convert samples with 8bit precision only since R2 > 5.65k. To convert with 16b precision, measured voltage impedance must not exceed 170R. To achieve the desired offset R1 value can be lowered accordingly but that requires considerable V1 current and very low source impedance. That is why the proposed solution should be used with particular caution and cannot be recommended as a standard approach if high conversion precision/resolution is required.

DS13195, table Table 93. ADC characteristics

[AScha.3]

@TDJ  , thats not correct in general, only for max. possible sampling speed. 

So for using a resistive input divider, lets look, how ADC is working and how its to be used (see AN2843).

We have to put a C (CAIN) at the ADC input (if not driving by low impedance buffer (opamp)).

Because ADC input is a small cap ( 5pF about) , thats switched to input at the sampling time we set.

This will result always in a "spike" at the input - we can calculate this :

So for 10k - 10k input divider (5k impedance at input) and C 22nF ->

we can use it up to 1kHz with "full" resolution.

So a resistive input divider (+ cer.cap , like 22nF ) can be used , if high conversion precision/resolution is required.

The important restrictive condition is : to use long enough sampling time, according to the impedance at the ADC input and the expected/needed precision.

Simply said : the higher the input impedance , the lower the frequency , which can be captured with "full" resolution.

+ see AN2843 for more detail.

[TDJ]

@AScha.3 Right, additional ~10-100nF capacitor added between ADC input and ground often sufficiently solves the problem. Another solution is adding "instrumentation amplifier" which allows for both gain and offset adjustment while bringing input impedance to giga ohms level. My favorite one is inexpensive but very capable INA823 i.e. used in my All-Purpose-Power-Micro-Controller although it does not directly solve this particular problem - required gain < 1 (attenuator). INA851 should do the job if needed gain is not smaller than 0.2 but it requires 8V (min) power supply. In most cases less expensive INA823, 350 or 351 with resistor divider and small capacitor added before ADC should provide an adequate solution. One note: op-amp capacitive load may cause instability - caution must be taken.
State-of-the-art solutions, at least conceptually, use two input stages: high impedance unity-gain buffer, resistor divider/attenuator optionally with level shifter, then another buffer/amplifier with low drift/offset often followed by a small <100R resistor and 1-10 nF capacitor.
However, in this thread I tried to simplify things, not to complicate them.