I am currently working on a H723 based HS USB device with external USB PHY (USB3320,USB3340,USB3300 tested).
While testing i have noticed that seemingly randomly between debug/flash cycles HS USB stops working with usually no activity on the bus but the HAL Phy setup usually still succeeds enabling the PHY but leading to an unknown device for the host.
After replacing the H7 everything works again indicating some internal damage. This has happened several times on different revisions each with other protection attempts already so i can rule out a random bad or damaged chip.
The closest matching report is this post hinting at possibly the weirdly unprotected analog switched PC2_C and PC3_C pins which are also present and used for DIR and NXT on the H723V.
There has never been activity on any ULPI pins coming from the STM after the initial HAL PHY setup with these damaged parts so damage within or behind the analog switch seems plausible that it does not see the NXT/DIR signals but could be something else. Once the Bus was stuck in a weird state with a high frequency signal only on the DP pin and NXT (ULPI was fine. Replacing H7 fixed it).
After this damage the internal USB still works.
DFU works and when reflashing to use the internal port instead of the HS ULPI was also successful. It seems to mostly affect the HS ULPI interface.
The debugger is an STlink v3 with the isolator addon. All external pins (and the _C and debug pins in one revision to be extra sure) are protected with clamping diodes.
The analog supply comes from the same 3.3V regulator as the main supply and USB phy supply. VREF+ is connected to VDDA and vrefbuf disabled. All analog inputs are connected to opamp buffers also powered by this same 3.3V supply and should not see any significant voltage spikes.
There are high power components on the same board but no damage or glitches have been observed during operation. The damage does likely occurs in the startup phase as it was never seen during operation and only after reflashing the chip.
Trying to reproduce possible voltage spikes during the reset state and capturing signals on possibly sensitive pins and supplies with a scope yielded no result yet.
So i would be very glad about any hint that might point me to a possible cause of these defects.
If there are any specific pins, startup conditions or anything where the chip is more vulnerable that might occur in such a configuration.
