Can I put read/write variables in DTCM, when DCache enabled?

[leon64]

If DCache is enabled how then can I update a variable (I think DMA + MDMA) and after processing get results to a peripheral e.g. DAC (again MDMA?)?

Do I need to clear cache?

Will I still have the speed advantage of caching?

I am struggling how to get data into and out of DTCM when DCache is enabled.

For data into DTCM it is my experience data is not updated and for data out of DTCM there is no updated data to export ( because of caching?)

I get data from my ADC via HAL_ADC_Start_DMA and have to start HAL_MDMA_Start_IT on every conversion completed. That seems to work. Is it the best way to go about it?

When I want to get data out of DTCM I use SCB_CleanInvalidateDCache_by_Addr and then update the DAC buffer. That seems to work but I do not trust the validity of the data.

Can anyone point me in the right direction?

[waclawek.jan]

> On this chip STM32H723 one can enable caching of ITCM and DTCM.

TCM are not cached.

 

JW

[FBL]

Thank you for the clarification @Community member​,

I suggest @leon64​ to transfer data only in D2 Domain and offloading CPU using DMA. Does this meet your requirements ?

[leon64]

Hi @F.Belaid​ 

I measure performance by toggling io pins and view/compare/measure with an oscilloscope.

Reading AN4891, I want to know how the address space is split up from the defines in the linker file. (I am referring to the numbers I put in the screenshot)

In the linker file these regions are defined

/* Specify the memory areas */

MEMORY

{

 ITCMRAM (xrw)   : ORIGIN = 0x00000000,  LENGTH = 64K

 DTCMRAM (xrw)   : ORIGIN = 0x20000000,  LENGTH = 128K

 FLASH   (rx)   : ORIGIN = 0x08000000,  LENGTH = 1024K

 RAM_D1 (xrw)   : ORIGIN = 0x24000000,  LENGTH = 320K

 RAM_D2 (xrw)   : ORIGIN = 0x30000000,  LENGTH = 32K

 RAM_D3 (xrw)   : ORIGIN = 0x38000000,  LENGTH = 16K

}

It is clear that ITCMRAM and DTCMRAM are 1) and 2)

But RAM D1, is that 3) and 4) or just 4)

And RAM D2, is that 5) and 6)

If I interpret the information from AN4891 correctly, I will get best performance by using ITCMRAM for code, DTCMRAM for lookup tables and AXI RAM for calculation variables. Hence my question about addressing, how do I specify variables to be located in AXI RAM?

And to come back to a previous post, if I were to use the DTCM caching and want to configure the MPU, is the code I posted correct? And if I want to split DTCM into a part that is cached and part that is not, do I then specify e.g. MPU_REGION_SIZE_64KB?

And do I then split DTCMRAM in the linker file into 2 regions?

[leon64]

That is fine! But the question remains where to put the variables for calculations for optimal performance.

[leon64]

Thank you!, I did not know.

[leon64]

That last question is now known to be a foolish question. So please ignore it.

[Tesla DeLorean]

Put or keep them in MCU registers, or in DTCM

[FBL]

Hello everyone,

It may help to think of additional relevant information.

TCMs always behave as Non-cacheable Non-shared Normal memory, irrespective of the memory type attributes defined in the MPU for a memory region containing addresses held in the TCM. It is mentioned in ARM v7-M Architecture Reference Manual