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Calculating pulse width (duty cycle) using stm32 DMA. Is it possible?

AKhor.1
Associate II

I'm working on a project that a series of duty cycles must be measured. A sample of related waveforms is displayed below:

0693W00000DpzmoQAB.png 

As you can see from the signal, the frequency is too high, and calculating it using bit functions is impossible. In the controller's tech website here, they used the timer's input capture modes and rising-falling edges interrupt for calculating the difference between two captures of the timer. But this method is too slow and cannot fulfill our desires for high-frequency signals. The other solution is to use DMA for fast transferring the capture data to the memory. But in STM32cubemx it is not possible to assign two DMAs for two captures of a timer as you can see below:

0693W00000DpzmtQAB.png 

Could someone give me a suggestion for this issue?

1 ACCEPTED SOLUTION

Accepted Solutions

Datasheet claims that you can use TIM3_CH1,TIM3_CH3,TIM3_CH4,TIM3_UP,TIM3_TRIG as DMA request sources. In your selection missing TIM3_CH3. Probably this is used by another peripheral. You can use TIM3_CH3 and TIM3_CH4 for your task, but you will need "unblock" DMA1 Channel2.

But if your PWM frequency is fixed you can use timer "PWM capture" mode (which need only one DMA request). You set up timer to reset by rising edge. And to "capture" (and DMA request) by falling edge. Every your input signal period start timer start counting from zero. Then capture time of falling edge carry all information about duty cycle (assuming you know frequency). this mode is usable only for CH1 and CH2.

If frequency is not fixed, then you need use two capture events. Again you can set timer to restart with rising edge. One channel to capture falling edge (signal pulse width) and second to capture rising edge (signal period). In that case you have to select another timer, with available DMA request for CH1 and CH2 events (TIM2,TIM4,TIM5,TIM8).

Table 78 and 79

https://www.st.com/resource/en/reference_manual/cd00171190-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf

View solution in original post

5 REPLIES 5

Which STM32?

There are timers which allow individual DMA on CH1 and CH2, so select such timer. Assignment of requests (triggers) to individual DMA channels is usually given in the DMA chapter of Reference Manual (RM) for given STM32 model.

JW

PS. Stackoverflow is certainly not the "controller's tech website" for STM32.

AKhor.1
Associate II

I'm using STM32F103RET6.

Datasheet claims that you can use TIM3_CH1,TIM3_CH3,TIM3_CH4,TIM3_UP,TIM3_TRIG as DMA request sources. In your selection missing TIM3_CH3. Probably this is used by another peripheral. You can use TIM3_CH3 and TIM3_CH4 for your task, but you will need "unblock" DMA1 Channel2.

But if your PWM frequency is fixed you can use timer "PWM capture" mode (which need only one DMA request). You set up timer to reset by rising edge. And to "capture" (and DMA request) by falling edge. Every your input signal period start timer start counting from zero. Then capture time of falling edge carry all information about duty cycle (assuming you know frequency). this mode is usable only for CH1 and CH2.

If frequency is not fixed, then you need use two capture events. Again you can set timer to restart with rising edge. One channel to capture falling edge (signal pulse width) and second to capture rising edge (signal period). In that case you have to select another timer, with available DMA request for CH1 and CH2 events (TIM2,TIM4,TIM5,TIM8).

Table 78 and 79

https://www.st.com/resource/en/reference_manual/cd00171190-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf

thanx

thanx