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Bugs in STM32G4, RM0440 Rev 7 for FDCAN

AVasi.11
Associate II

Bugs in STM32G4, RM0440 Rev 7 for FDCAN:

1)

STM32G4, RM0440 Rev 7  44.3.3 Message RAM.

It is written on the page 1953:

"In case of multiple instances the RAM start address for the FDCANn is computed by end

address + 4 of FDCANn-1, and the FDCANn end address is computed by FDCANn start

address + 0x0350 - 4.

As an example, for two instances:

• FDCAN1:

– start address 0x0000

– end address 0x0350 (as in Figure 669)

• FDCAN2:

– start address = 0x0350 (FDCAN1 end address) + 4 = 0x0354

– end address = 0x0354 (FDCAN2 start address) + 0x0350 - 4 = 0x06A0"

This is not true. In fact

• FDCAN1:

– start address 0x0000

– end address 0x0350 - 4 (as in Figure 669)

• FDCAN2:

– start address 0x0350 (FDCAN1 end address) + 4 = 0x0350

– end address = 0x0350 (FDCAN2 start address) + 0x0350 - 4 = 0x069С

I checked on the NUCLEO-G474. Code is working correctly

#define FDCAN1_MEM_START_ADDR           0x4000A400UL

#define CAN_RAM_SIZE                                 0x350UL          

#define FDCAN2_MEM_START_ADDR           (FDCAN1_MEM_START_ADDR + CAN_RAM_SIZE)

#define SIZE_FIFO_TX (64+8)

#define ID_Master                                          0x019B1AFUL

uint8_t TX_index;

TX_index = (uint8_t)((FDCAN2->TXFQS >> 8) & 0x3);     //Tx FIFO get index

uint32_t *pFifo = (uint32_t*)(FDCAN2_MEM_START_ADDR + CAN_TXBUF + TX_index*SIZE_FIFO_TX);

*pFifo = ID_Master;                                //Load ID

*pFifo |= 1 << 30;                                   //29-bit extended identifier

*pFifo++;

*pFifo++ = (14 << 16) | (1<<21);           //48 send Byte | FDCAN frame format

If you set FDCAN2_MEM_START_ADDR = FDCAN1_MEM_START_ADDR + 0x354, the transfer is incorrect

***********************************************************************************

2)

STM32G4, RM0440 Rev 7, page 85

 0693W00000bhBWbQAM.pngThe FDCANs Message RAM addresses, for example FDCAN1  “0x4000 A400 - 0x4000 A7FF�? are incorrect, there are no 1 KB sections, it should be 0x0350 B.

Also the FDCANs Message RAM area in the table is not related to the FDCAN register map

3 REPLIES 3
KDJEM.1
ST Employee

Hello @AVasi.11​ ,

Thank you for reporting this issue.

I will check internally and I will back to you as soon as possible.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

AVasi.11
Associate II

I also got an error :) , in the line you need to read

• FDCAN2

– start address 0x0350 - 4 (FDCAN1 end address) + 4 = 0x0350

KDJEM.1
ST Employee

Hi @AVasi.11​ ,

The first issue is already reported here.

The correct values of FDCAN addresses ranges are:

• FDCAN1:

– start address 0x0000

– end address 0x0350 - 4=0x34C (as in Figure 669)

• FDCAN2:

– start address 0x034C (FDCAN1 end address) + 4 = 0x0350

– end address = 0x0350 (FDCAN2 start address) + 0x0350 - 4 = 0x069С

This issue reported internally.

Internal ticket number 123624 is submitted (This is an internal tracking number and is not accessible or usable by customers).

Thanks

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.