I2S BUS acting weird when using FWS = 196KHz

[CLeo.1]

Hi guys, Ill keep this short, anytime I set the I2S bus to use FWS = 196KHz it acts all whack.

I am not sure if its the tool I am measuring with but its a saleae logic analyzer so I doubt it.

Here a picture of what I am talking about

I double checked everything the clock config is correct, I double checked with other FWS work such as 96,48, and 44.1 KHz and they are all fine

The GPIOs are using the "Very High Speed" Setting as well

Code

/*
 * AUDIO_SELECTOR_FACTORY.c
 *
 *  Created on: May 3, 2021
 *      Author: Christopher
 */
 
#include <CONSTANTS.h>
#include "stm32h753xx.h"
#include "Opcode.h"
 
void INPUT_AUDIO_SELECTOR (int INPUT_TYPE, int BIT_RATE, int SAMPLING_RATE) {
	RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN);
 
	//DECONFIG I2S
	DMA1_Stream0->CR &= ~DMA_SxCR_EN;
	DMA1_Stream1->CR &= ~DMA_SxCR_EN;
	SPI1->CR1 &= ~SPI_CR1_SPE;
	SPI1->CR1 &= ~SPI_CR1_CSTART;
	RCC -> CR &= ~(RCC_CR_PLL2ON);
 
	//CONFIG I2S
 
	switch (SAMPLING_RATE) {
 
	case 192000:
 
		RCC -> PLLCKSELR &= ~(RCC_PLLCKSELR_DIVM2);
		RCC -> PLLCKSELR |=  (RCC_PLLCKSELR_DIVM2_DIV10);
 
	    RCC -> PLL2FRACR = 0;
		RCC -> PLL2FRACR = (RCC_PLL2FRACR_FRACN2_7209);
 
		RCC -> PLLCFGR   &= ~((RCC_PLLCFGR_PLL2VCOSEL) |
							  (RCC_PLLCFGR_PLL2RGE)    |
							  (RCC_PLLCFGR_PLL2FRACEN) |
							  (RCC_PLLCFGR_DIVP2EN)    |
							  (RCC_PLLCFGR_DIVQ2EN)    |
							  (RCC_PLLCFGR_DIVR2EN));
 
		RCC -> PLLCFGR   |= (RCC_PLLCFGR_PLL2VCOSEL_WIDE_RANGE) |
						    (RCC_PLLCFGR_PLL2RGE_8MHz_16MHz)    |
						    (RCC_PLLCFGR_DIVP2EN)               |
						    (RCC_PLLCFGR_PLL2FRACEN);
 
		RCC -> PLL2DIVR  &= ~((RCC_PLL2DIVR_N2) |
							  (RCC_PLL2DIVR_P2));
 
		RCC -> PLL2DIVR  |= (RCC_PLL2DIVR_N2_122) |
							(RCC_PLL2DIVR_P2_4);
		       break;
	case 96000:
 
		RCC -> PLLCKSELR &= ~(RCC_PLLCKSELR_DIVM2);
		RCC -> PLLCKSELR |=  (RCC_PLLCKSELR_DIVM2_DIV10);
 
		RCC -> PLL2FRACR = 0;
		RCC -> PLL2FRACR = (RCC_PLL2FRACR_FRACN2_7209);
 
		RCC -> PLLCFGR   &= ~((RCC_PLLCFGR_PLL2VCOSEL) |
							  (RCC_PLLCFGR_PLL2RGE)    |
							  (RCC_PLLCFGR_PLL2FRACEN) |
							  (RCC_PLLCFGR_DIVP2EN)    |
							  (RCC_PLLCFGR_DIVQ2EN)    |
							  (RCC_PLLCFGR_DIVR2EN));
 
		RCC -> PLLCFGR   |= (RCC_PLLCFGR_PLL2VCOSEL_WIDE_RANGE) |
						    (RCC_PLLCFGR_PLL2RGE_8MHz_16MHz)    |
							(RCC_PLLCFGR_DIVP2EN)               |
							(RCC_PLLCFGR_PLL2FRACEN);
 
		RCC -> PLL2DIVR  &= ~((RCC_PLL2DIVR_N2) |
							  (RCC_PLL2DIVR_P2));
 
		RCC -> PLL2DIVR  |= (RCC_PLL2DIVR_N2_122) |
							(RCC_PLL2DIVR_P2_8);
		      break;
	case 48000:
 
		RCC -> PLLCKSELR &= ~(RCC_PLLCKSELR_DIVM2);
		RCC -> PLLCKSELR |=  (RCC_PLLCKSELR_DIVM2_DIV4);
 
		RCC -> PLL2FRACR = 0;
		RCC -> PLL2FRACR = (RCC_PLL2FRACR_FRACN2_1835);
 
		RCC -> PLLCFGR   &= ~((RCC_PLLCFGR_PLL2VCOSEL) |
							  (RCC_PLLCFGR_PLL2RGE)    |
							  (RCC_PLLCFGR_PLL2FRACEN) |
							  (RCC_PLLCFGR_DIVP2EN)    |
							  (RCC_PLLCFGR_DIVQ2EN)    |
							  (RCC_PLLCFGR_DIVR2EN));
 
	    RCC -> PLLCFGR   |= (RCC_PLLCFGR_PLL2VCOSEL_WIDE_RANGE) |
						    (RCC_PLLCFGR_PLL2RGE_8MHz_16MHz)    |
						    (RCC_PLLCFGR_DIVP2EN)               |
						    (RCC_PLLCFGR_PLL2FRACEN);
 
	    RCC -> PLL2DIVR  &= ~((RCC_PLL2DIVR_N2) |
							  (RCC_PLL2DIVR_P2));
 
	    RCC -> PLL2DIVR  |= (RCC_PLL2DIVR_N2_52) |
						    (RCC_PLL2DIVR_P2_17);
			   break;
	case 44100:
 
		RCC -> PLLCKSELR &= ~(RCC_PLLCKSELR_DIVM2);
		RCC -> PLLCKSELR |=  (RCC_PLLCKSELR_DIVM2_DIV4);
 
		RCC -> PLL2FRACR = 0;
		RCC -> PLL2FRACR = (RCC_PLL2FRACR_FRACN2_1835);
 
		RCC -> PLLCFGR   &= ~((RCC_PLLCFGR_PLL2VCOSEL) |
							  (RCC_PLLCFGR_PLL2RGE)    |
							  (RCC_PLLCFGR_PLL2FRACEN) |
							  (RCC_PLLCFGR_DIVP2EN)    |
							  (RCC_PLLCFGR_DIVQ2EN)    |
							  (RCC_PLLCFGR_DIVR2EN));
 
		RCC -> PLLCFGR   |= (RCC_PLLCFGR_PLL2VCOSEL_WIDE_RANGE) |
							(RCC_PLLCFGR_PLL2RGE_8MHz_16MHz)    |
							(RCC_PLLCFGR_DIVP2EN)               |
							(RCC_PLLCFGR_PLL2FRACEN);
 
		RCC -> PLL2DIVR  &= ~((RCC_PLL2DIVR_N2) |
							  (RCC_PLL2DIVR_P2));
 
	    RCC -> PLL2DIVR  |= (RCC_PLL2DIVR_N2_28) |
							(RCC_PLL2DIVR_P2_10);
	           break;
 
	}
 
	RCC -> D2CCIP1R &= ~(RCC_D2CCIP1R_SPI123SEL);
	RCC -> D2CCIP1R |=  (RCC_D2CCIP1R_SPI123SEL_PLL2_P_CK);
 
	RCC -> CR &= ~(RCC_CR_PLL2ON);
	RCC -> CR |=  (RCC_CR_PLL2ON);
 
	while (!((RCC -> CR) & (RCC_CR_PLL2RDY)));
 
 
	SPI1->I2SCFGR = 0x00;
    SPI1->CFG1 &= ~((SPI_CFG1_RXDMAEN) |
					(SPI_CFG1_TXDMAEN));
 
					 SPI1->CFG1 |= (SPI_CFG1_RXDMAEN) |
					               (SPI_CFG1_TXDMAEN);
		             SPI1->I2SCFGR |= (SPI_I2SCFGR_MCKOE)              |
							          (SPI_I2SCFGR_I2SDIV_2)           |
							          (SPI_I2SCFGR_DATFMT_LEFT)        |
							          (SPI_I2SCFGR_I2SSTD_I2S)         |
							          (SPI_I2SCFGR_I2SCFG_MASTER_FULL) |
							          (SPI_I2SCFGR_I2SMOD_I2S);
 
	switch (INPUT_TYPE) {
 
	case INPUT_INLINE:
		//Disable everything else besides INLINE
		break;
 
 
	case INPUT_BLUETOOTH:
		 //Disable everything else besides BT
		break;
	}
 
	switch (BIT_RATE) {
 
    case 16:
			SPI1->I2SCFGR |= (SPI_I2SCFGR_DATLEN_16BIT);
			SPI1->I2SCFGR |= (SPI_I2SCFGR_CHLEN_32BIT);
			break;
 
    case 24:
			SPI1->I2SCFGR |= (SPI_I2SCFGR_DATLEN_24BIT);
			SPI1->I2SCFGR |= (SPI_I2SCFGR_CHLEN_32BIT);
			break;
 
		}
 
	 DMA1_Stream0->CR |= DMA_SxCR_EN;
	 DMA1_Stream1->CR |= DMA_SxCR_EN;
	 SPI1->CR1 |= SPI_CR1_SPE;
	 SPI1->CR1 |= SPI_CR1_CSTART;
}

[waclawek.jan]

What is " acts all whack"? What do we see on that picture?

Read our and check/post the relevant I2S/SPI registers content.

JW

[CLeo.1]

Sorry, I could have explained my self better.

In that picture from the top to bottom is:

1. FW
2. SCLK
3. MCLK

These are signals from the I2S Bus

Yup, I checked all the ideal regs and they are all setting properly. Like I mentioned above when using FWS = 44.1, 48, or 96 KHz they are fine, and what I mean by fine the signals are continuous, there arent large gaps like shown in the picture posted above. In the picture even the frequencies arent set right, FW in the picture says its 50KHz

[waclawek.jan]

Looks more like noise/inconsistent grounds.

JW

[CLeo.1]

Yup I think you nailed it, just tried doing the other FWS now it looks like the same the 196KHz, how do I go by fixing this, I am grounding the measuring tool I dont know what else to do

[CLeo.1]

Just an update, plugged it into a separate computer the logic analyzer and its much better however, 96 and 192 KHz still not good

[waclawek.jan]

What is "still not good"?

JW

[CLeo.1]

Showing the same behavior as in the picture, thats what I mean still not good. Not good as in not the standard, not good as in theres something still wrong with it, not good as in its not what an I2S bus should look like.