I have the FMAC working enough to produce values readable from RDATA, but they are acting strangely and giving small positive and negative values and 0. As a minimal test, I created the below code to have X1 and X2 be all 1s. A buffer length of 18 should produce an FIR result of 18. The below code produces a result of 0 which I read out via STLink from an unused register on TIM20.
If I let my code to progress such that X1 contains real changing data, the RDATA value changes minutely above and below zero.
I suspect I have addressing errors of some sort, but if I loaded only 1s into everything, I should still get 18...?
Did I miss anything in the below code?
//FMAC Config
FMAC->X1BUFCFG = 0x000012DC; //no threshold, 18 buffer length, 220 as base address.
FMAC->YBUFCFG = 0x000001FF; //no threshold, 1 buffer length, 255 base address.
FMAC->CR|=0x00010000;//reset
//write X2 vectors..18 long 12 total: 0-204 in FMAC mem
for(int i=0;i<12;i++){
FMAC->X2BUFCFG = 0x00001200+i*18;//increment base address w/ 18 buffer size
FMAC->PARAM = 0x82000012; //FUNC=2, P= 18, Q=0, R=don't care, Start =1
for(int j=0;j<18;j++){
FMAC->WDATA=0x1;
};
}
FMAC->X2BUFCFG = 0x00001200;//reset X2 base address
//LOAD X1 and check if it's full
FMAC->PARAM = 0x81000012; //FUNC=1, P=18 coeff, Q=dont care, R=don't care, Start =1
for(int j=0;j<18;j++){
FMAC->WDATA=0x1;
};
//X1Full does trip until the FIR op is enabled
FMAC->PARAM = 0x88000012; //FUNC=8, P=18 coeff, Q=dont care, R=0=gain, Start =1
while(FMAC->SR = !(FMAC->SR & 0x00000002)){};//second bit is X1full...wait until it is set
while(FMAC->SR & 0x00000001){};//Y is a single buffer, so Yempty goes low when the first value is present
TIM20->CCR5=FMAC->RDATA;
FMAC->CR|=0x00010000;//reset
