Problem with high speed in a custom board with STM32H735IGT6

[JVale.2]

Hi.

I am Jose Manuel. We have developed a custom board where the MCU is STM32H735IGT6, the external SRAM is APS12808L-3OBMX-BA and the external flash is W25Q128JVEIM.

The problem is that we want to work with 100 MHz, but it does not work, it just work up to 60 MHz.

We have developed a board with four levels, the same lenghts in the route and the same vias. Below, attached the interface between the SRAM and MCU. Could you please tell us what steps we have not done? Whats the recommendation to follow?

Thanks you and Best regards,

José Manuel

[Tesla DeLorean]

Even with uniform length the lines are probably still ringing / reflecting. Could can change the drive strength on the STM32 side via SPEEDR GPIO setting. Given the short length you can likely back that off significantly. Check the drive level on the W25Q side also, but likely to be low.

High speed designs would tend to have series resistors in the 27 / 33 R range to dampen the reflections and improve the matching.

The choice of command and dummy cycles can impact the burst speed as it can prefetch the page. Check also usability of DTR/DDR modes.

Caching can hide performance of the Flash NOR reading

[Tesla DeLorean]

Think of SPEEDR as a slew rate control, assuming certain loading and not just a "frequency" which ST implies. This is more about the energy being dumping into the lines, which in this case are apt to be very short, perhaps 40-50mm. You want a fast enough edge, just not all the ringing and overshoot.

ie don't use the 100 MHz settings just because that's what you think you want / need.

[BobWalance]

The 27-33ohm resistors that were mentioned by @Tesla DeLorean are very critical (assuming you have 50ohm traces). This type of termination is referred to as "source termination". They are used only for signals that have one source pin and one destination pin, and this is most common in fast-edge-rate designs.

The goal is to have the voltage level at the source (e.g., 3.3V) reach the destination pin at full voltage level (e.g., 3.3V), and also to not have any reflections reach the destination pin.

This is achieved because at the far side of the resistor, the voltage is "launched" into the transmission line at 3.3V/2.

When the waveform reaches the open-circuit at the end of the trace, the voltage is doubled from 3.3V/2 to a full 3.3V due to its full reflection back to the source. The end-reflected wave will be absorbed by the resistance of the source resistor (plus the output impedance of the driver).

This type of termination has the advantage of not having to tweak the drive strength at the source such that it is "just right". You want to make the drive as strong as possible, so you will meet your timing margins without worrying about multiple reflections. 

[JVale.2]

Hello,

Thanks for your replys.

The resistors are 33 ohms, only we have modified the resistor of the CLK to 250 ohms because it works better.

We think that the problem is in the impedance because the width of the routes is 0.2mm, so according to the impedance calculation it is 39 ohms. The possible solution is to modify the width to 0.13mm (50 ohms).

What's your opinion?

Best regards,

José Manuel

[Tesla DeLorean]

Not clear if your issue is one of signal integrity, stubs or interactions between the STM32, RAM and FLASH devices.

Check you're using the right commands and modes for the bandwidth expected.

[Tesla DeLorean]

Perhaps provide salient portions of schematics, initialization code, and data patterns showing success and failure situations? How much data reads correctly at higher speeds?

[LCE]

One more point, just to make sure: do all the signal layers have a directly neighbouring und unbroken ground plane?

Impedance is hard to control, if it is 39 Ohm in real life, try changing the resistor values. 250 Ohm in the clock line "feels" a little high. It should have the same characteristics as the other control and data lines.

And here we have the disadvantage of the big QFP package, the signals are so far apart... Maybe some crosstalk from other high speed signals? The equal-length meandering can have some drawbacks.

[JVale.2]

Hello everyone,

Data is read correctly up to 60 MHz, above 60 MHz it is not read correctly. We have spent time on the codes and we have gotten this far. We need 100 MHz to work well on a 5" sceen (with 60 MHz and a 3.5" screen, it works well).

So, we think the failure is in HW and we are going to start modifying the PCB design following the guidelines from the AN4661 document (section 8.4.3). We have answers about it:

* Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR and GND). Where do we put it? The PCB is layer 1-TOP, layer 2-GND, layer 3-PWR and layer 4-BOTTOM.

* Trace the impedance: 50Ω ± 10%. We think our actual design impedance is 36-39 ohm, can we modify the resistors in our actual PCB to increase the impedance to 50 ohms? If so, how?.

Thanks you and Best regards,

José Manuel

[LCE]

You should increase the PCB track impedance slightly up to 50R. If your PCB software cannot calculate the width for you, there are many calculators online.

Resistor placement: they should be close to the source, which is not to determine for the data IOs, but you should put at least the resistors for CLK, DQS, NCS close to the MCU. Just as I write this , I see that on the H735 Discovery Board they put all the resistors close to the HyperRAM, and that is working here with 100 MHz.
So I don't know...