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How can I calculate the exact Audio frequency of a MEMS microphone?

Associate II


I developed an application that uses an STM32L452 and MP34DT06J, with SPI and DMA. I don't have an external clock on the MCU so I'm using the internal one. Regarding the storage, I'm using an external Micro SD driven with SDMMC.

Since I've more sensors acquiring at the same time, for me it's extremely important to know the exact frequency of the signals since it can lead to a misalignment of the signals. When I was recording sound with my application and comparing it with my smartphone, I found that the sampling frequency isn't exactly 16kHz. So the questions are:

  1. How can I find the exact frequency?
  2. Does the internal clock allow me to have a constant sampling frequency, with drift over time?

Best Regards

ST Employee

Welcome, @Community member​, to the community!

The internal clock used for the PDM data stream is derived from the external clock at CLK (AN5027):

PDM modulator converts the buffered analog signal into a serial pulse density modulated signal. The clock input (CLK) is used to control the PDM modulator. The clock frequency range for ST digital microphones is from 1 MHz to 3.25 MHz. This frequency defines the sampling rate at which the amplifier’s analog output signal is sampled to produce a discrete-time representation (PDM bitstream).

So if your application with the STM32L452 uses internal, free-running clock sources, the sampling frequency cannot be more accurate than those clock sources.

Does this answer your question?



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Associate II

Hi @Peter BENSCH​ 

Thank you for your prompt response.

So if the internal clock source is inaccurate, the audio sampling frequency will always be inaccurate too. That's the reason why I can't find the exact clock frequency. Is that right?


However, all connected microphones follow the same frequency (if they are using the same clock) and behave identical to each other, which might help you in your application?



In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

In my specific case, the sensorial specs are:

  • A microphone connected with SPI, with DMA.
  • ADC to acquire data from an analog sensor.
  • I2C for an ST's Accelerometer.

These three sources of data are being stored in the SDCard and I need all these three completely aligned. For that, I need to know the exact audio frequency. So, it's not important if I have an audio frequency of 16kHz or 16.55KHz. However, it must be constant over time.

I'm thinking about adding an HSE and changing the mic's peripheral to I2S with SAI. In this application note it's stated that with I2S, with mono channel, I can reach accuracies of 0ppm. Do you think it can solve my problem?

I really appreciate you feedback

Absolutely use an external clock source.

From all the internal RC oscillators that I have seen in STM32F7, H7, G4 none was usable for audio better than 12 bit.

But not due to tha inaccuracy, but the high jitter.

A peak-to-peak jitter on F7 PLL is 200 ps. At 20 kHz it gives 92 dB SNR, which corresponds to 15,3 bits.

One gets a 12-bit resolution or 72 dB at 200 kHz... Maybe there was a calculation error regarding 20 vs 200 kHz?

Senior III

Not sure if this helps. But I need accurate timing from the PDM microphone for tuning purposes. The DFSDM is driven by a non-crystal clock. So I DMA the output of the DFSDM to a single location, then I use the accurate 32,768Hz LSE to drive a timer to sample that data from that memory location and transfer it to a buffer - works for me, my tuner is spot on accurate.

The PLL is not the problem, it's the internal RC oscillator.

I did some tests with F767 and its SAI in TX SPDIF mode and a generated 32bit sinus. (I actually use that all the time now for testing)

I can't remember the details, but signal quality HSI vs HSE was terrible.

With the HSE and PLL and TX SPDIF @ sample rate 200 kHz going into a Crystal SRC and SPDIF receiver (CS8422) noise and THD were seemingly limited only by the receiver (THD & SNR > 120 dB).

On several Nucleo boards, also with a H7 and G4.

So that PLL spec of 200 ps seems to be a maximum at temperature limits, maybe also depending on the chosen dividers and multipliers.

@Community member​ 

That's interesting, is there any HSI / clock calibration with the LSE involved?

Because I cannot see how sampling data with accurate timing from memory location after DMA might help with exact sampling rates?