Official library for LIS3DH with FIFO DMA transfer

[tcg]

HI, I am trying to develop a application with a accelerometer over 5kHz.

I have some samples of LIS3DH. Does exits any repository of mem senc?

I search in cubemx but is not there.

I can write the library from datasheet but it is a lot of time and it will not be mantain.

do you know if other device in cubemx or in c official library is supported by st?

I am interested on fifo DMA transfer by I2c .

Thanks fot all, tcg

[WojtekP1]

It's just I2C transfer. Can't you do anything yourself instead of just library&cut&paste?

PS. Works perfect. i used LIS3DH

[tcg]

yes of course, but as I said, I would prefer to know if there is an official library for maintenance and integration.

Kind regards, tcg

[Eleon BORLINI]

Hi @Tomás Cabeza​ ,

There is a C example for FIFO configuration on LIS3DH on Github, you can find it at this link --> lis3dh_multi_read_fifo.c.

Then once you have the data from the FIFO, you can implement the DMA transfer through STM32 / CubeMX libraries.

-Eleon

[tcg]

Thanks a lot @Eleon BORLINI​ .

I will try this code tomorrow. I will give you a feedback

Thanks a lot for your fast response, tcg

[tcg]

HI @Eleon BORLINI​ 

That works, 1) I have just understand that DMA have no sense with I2C becouse a fifo reading for 192 bytes is the same, is not it?

is it possible create a dma for this? The difference iss that the processor is free during the i2c transaction.

I am trying to make a i2c reading of 192 i2c after int1 event is detected. That event could be with ov or watermaker 2/3 fifo.Is that correct?

2) LIS3DH is not real 5kHz Bw is only OutputSR. Does it exits any device in st roadmap with (>3-4kHz BW) >OSR?

kind regards, tcg

2)

[tcg]

​ Hi @Eleon BORLINI​ 

That seems that work well.

But I am not able to control the INT1 with watermark o ov fifo. Any idea?

It is a little spaguetti code...

Thanks for all.

-----

/* Initialize mems driver interface */

 stmdev_ctx_t lis3dh_ctx;

 lis3dh_ctx.write_reg = platform_write;

 lis3dh_ctx.read_reg = platform_read;

 lis3dh_ctx.handle = &SENSOR_BUS;

 lis3dh_reg_t LIS3DH_reg;

 /* Check device ID */

 lis3dh_device_id_get(&lis3dh_ctx, &whoamI);

 /* Enable Block Data Update */

 lis3dh_block_data_update_set(&lis3dh_ctx, PROPERTY_ENABLE);

 //CTRL_REG1 (20h)

 // ODR [3:0] -> Set Output Data Rate

 lis3dh_data_rate_set(&lis3dh_ctx, LIS3DH_ODR_5kHz376_LP_1kHz344_NM_HP );

 /* Set operating mode to high resolution */

 lis3dh_operating_mode_set(&lis3dh_ctx, LIS3DH_LP_8bit);

 //CTRL_REG2 (21h)

 //HPM[1:0] High-pass filter mode selection. Default value: 00Refer to Table 34: High-pass filter mode configuration

 //HPCF[2:1] High-pass filter cutoff frequency selection

 //FDS Filtered data selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register and FIFO)

 //HPCLICK High-pass filter enabled for CLICK function.(0: filter bypassed; 1: filter enabled)

 //HP_IA2 High-pass filter enabled for AOI function on interrupt 2, (0: filter bypassed; 1: filter enabled)

 // HP_IA1 High-pass filter enabled for AOI function on interrupt 1, (0: filter bypassed; 1: filter enabled)

  uint8_t high_pass_on_outputs_value;

   lis3dh_high_pass_on_outputs_get(&lis3dh_ctx,&high_pass_on_outputs_value);

 //CTRL_REG3 (22h)

 LIS3DH_reg.ctrl_reg3.i1_321da=0;

 LIS3DH_reg.ctrl_reg3.i1_click=0;

 LIS3DH_reg.ctrl_reg3.i1_ia1=0;

 LIS3DH_reg.ctrl_reg3.i1_ia2=0;

 LIS3DH_reg.ctrl_reg3.i1_overrun=1; // FIFO overrun interrupt on INT1. 1: enable

 LIS3DH_reg.ctrl_reg3.i1_wtm=1;   // FIFO watermark interrupt on INT1. 1: enable

 LIS3DH_reg.ctrl_reg3.i1_zyxda=0;

 lis3dh_pin_int1_config_set(&lis3dh_ctx,&LIS3DH_reg.ctrl_reg3);

 //CTRL_REG4 (23h)

 // FS[1:0] Full-scale selection. (00: ±2 g; 01: ±4 g; 10: ±8 g; 11: ±16 g)

 lis3dh_full_scale_set(&lis3dh_ctx, LIS3DH_2g);

 //HR High-resolution output mode (0: high-resolution disabled; 1: high-resolution enabled)

 // FIFO

 lis3dh_op_md_t mode;

 lis3dh_operating_mode_get(&lis3dh_ctx, &mode);

 /* Set FIFO watermark to 25 samples */

 lis3dh_fifo_watermark_set(&lis3dh_ctx, 25);

 int8_t watermark;

 lis3dh_fifo_watermark_get(&lis3dh_ctx, &watermark);

 //FIFO_CTRL_REG (2Eh)

 // FM -> Set FIFO mode to Stream mode: Accumulate samples and override old data */

 lis3dh_fifo_mode_set(&lis3dh_ctx, LIS3DH_DYNAMIC_STREAM_MODE); //LIS3DH_STREAM_TO_FIFO_MODE

 //TR -> Trigger selection; 0: Int1, 1: Int2

 lis3dh_fifo_trigger_event_set(&lis3dh_ctx,LIS3DH_INT1_GEN);

 lis3dh_tr_t INT_Selected;

 lis3dh_fifo_trigger_event_get(&lis3dh_ctx,&INT_Selected);

 //CTRL_REG5 (24h)

 //FIFO_EN

 lis3dh_fifo_set(&lis3dh_ctx, PROPERTY_ENABLE);

//INT_POLARITY INT1 and INT2 pin polarity. Default value:

 //lis3dh_read_reg(&dev_ctx,0,&LIS3DH_reg);

  lis3dh_ble_t dataformat_value;

  lis3dh_data_format_get(&lis3dh_ctx,&dataformat_value);

 // Disable all interrupt events from x,y,z

 //INT1_SRC (31h)

 LIS3DH_reg.int1_cfg._6d=0;

 LIS3DH_reg.int1_cfg.aoi=1;

 LIS3DH_reg.int1_cfg.xhie=0;

 LIS3DH_reg.int1_cfg.xlie=0;

 LIS3DH_reg.int1_cfg.yhie=0;

 LIS3DH_reg.int1_cfg.ylie=0;

 LIS3DH_reg.int1_cfg.zhie=0;

 LIS3DH_reg.int1_cfg.zlie=0;

 lis3dh_int1_gen_conf_set(&lis3dh_ctx, &LIS3DH_reg.int1_cfg);

 lis3dh_int1_gen_conf_get(&lis3dh_ctx, &LIS3DH_reg.int1_cfg);

 //INT2_CFG (34h)

 LIS3DH_reg.int2_cfg._6d=0;

 LIS3DH_reg.int2_cfg.aoi=1;

 LIS3DH_reg.int2_cfg.xhie=0;

 LIS3DH_reg.int2_cfg.xlie=0;

 LIS3DH_reg.int2_cfg.yhie=0;

 LIS3DH_reg.int2_cfg.ylie=0;

 LIS3DH_reg.int2_cfg.zhie=0;

 LIS3DH_reg.int2_cfg.zlie=0;

 lis3dh_int2_gen_conf_set(&lis3dh_ctx, &LIS3DH_reg.int2_cfg);

 lis3dh_int2_gen_conf_get(&lis3dh_ctx, &LIS3DH_reg.int2_cfg);

 //INT2_SRC (35h) -> interrupt state

 //INT2_THS (36h) -> level of mg event

 //INT2_DURATION (37h)-> event duration

 while (1)

 {

 lis3dh_fifo_status_get(&lis3dh_ctx, &LIS3DH_reg.fifo_src_reg);

 if (LIS3DH_reg.fifo_src_reg.ovrn_fifo==1){

lis3dh_int1_gen_conf_get(&lis3dh_ctx, &LIS3DH_reg.int1_cfg);

platform_delay(2);

lis3dh_fifo_status_get(&lis3dh_ctx, &LIS3DH_reg.fifo_src_reg);

 }