STM32 MCUs

I have been working with the single core LoRaWAN_End_Node example application on a B-WL5M-SUBG1 board with good success.  With STM32CubeMx v6.16.0, WL Firmware 1.4.0, I see a current draw of under 2uA between transmissions.Last week I upgraded STM32CubeMx to v6.17.0 which in turn upgraded the WL Firmware to 1.5.0, changed the end node example to use the LBM library rather than the LmHandler for managing the radio, and changed the example application name to LoRaWAN_End_Node_LBM.  The application functionality is good but the power consumption jumped to around 80uA between transmissions.In both cases I configured pullups in the USART2 pins (PA2, PA3).I can alternate between these two versions of the application on the same board and the results are very consistent.Has anyone else seen this and does anyone have any suggestions?

Hello, I am re-posting this.My original post on the old forums seems to have disappeared !?!I have prepared an SFI (with firmware, debug authentication key and option bytes)After SFI I want to boot to address 0x0C000000To achieve this I have programmed Option Bytes:BOOT_UBE = 0xB4 (OEM-iROT)TZEN = 0xB4PRODUCT_STATE = 0x72 (closed)(and some other bytes) After (successful ??) SFI, the Option Bytes are not programmed correctlyIt seems that SFI terminated early. PRODUCT_STATE is 0x17, UBE = 0xC3 Programming log is attached Am I being stupid? Am I missing something…? Note : I cannot attach the programming log because the attach feature does not work anymore. But it’s not really a useful feature anyway right? Who needs it. So I have made a copy-paste instead. 14:18:32 : Requesting Chip Certificate from device ...14:18:32 : Reading chip Certificate finished14:18:32 : Get Certificate done successfully14:18:32 : requesting license for the current STM32 device14:18:32 : Init Communication ... 14

I’ve followed the instructions for the STM32WB55 as a BLE sniffer, but I cannot get the st_ble_sniffer.py script to recognize my device as a BLE sniffer for usage in wireshark. Is this supported at all? Or are slight modifications required to make this work? As far as I can the tell the --extcap-interfaces should list all capable interfaces, but even the output example here does not list any example. The current result is that there is no entry in wireshark to use the STM as a sniffer.I’ve already tried updating the internal device.pid to 14163 instead of 14155 to account for the updated integrated ST-LINKv3

I am having trouble connecting to the STM32N6 with SWD.I have implemented a design using the STM32N645X0H3Q (though I have placed the STM32N647X0H3Q) using external VDDCORE. R110 is not mounted (to set VLXSMPS to NC).On startup I have VDDIO (3.3V) and VDDA1V8ON (1.8V) to the MCU, and the MCU activated PWR_ON (I have VDDA1V8ON to the PDR_ON pin, A1 on another page). This activates the reset of the power, including VDDCORE. All voltage measurements are as expected on the board.When I try to connect to the board using SWD in STMProgrammer (v2.20.0), I see the 3.3V, but the STMProgrammer does not connect. I am using a Minnie V3 (v V3J16M8) on Windows. I have tried lower frequencies and all modes and reset modes without success. I should mention that on my prototype board, I have not mounted external crystals, flash or ram. Though I believe that is not necessary for STMProgrammer to see the MCU. Any help is greatly appreciated!

In many NetX Duo Ethernet sample projects, HAL_ETH_Start_IT() is not called depending onthe timing of the PHY link‑up. When this happens, Ethernet communication never starts.The behavior appears to be related to how App_Link_Thread_Entry() handles link status:- nx_ip_interface_status_check() is used to check the NX_IP_LINK_ENABLED status.- nx_ip_driver_direct_command() issues NX_LINK_ENABLE or NX_LINK_DISABLE when the PHY link state changes.Normal behavior- If the PHY is link-up at startup, HAL_ETH_Start_IT() is called during initialization.- If the PHY is link-down at startup, App_Link_Thread_Entry() later detects the link-up,  issues NX_LINK_ENABLE, and HAL_ETH_Start_IT() is called correctly.Problem caseIf the PHY is link-down at startup but becomes link-up before App_Link_Thread_Entry() starts running:- The thread does not issue NX_LINK_ENABLE or NX_LINK_DISABLE.- HAL_ETH_Start_IT() is not called.- Ethernet communication cannot be established.In PoE environments, the power‑on to lin

When I connected an original board with STM32WBA5MM chip mounted to an STM32Cube Prog via ST-LINK, the message DEV_UNKNOWN_MCU_TARGET was output. Checking the JTAG signals, the DP_DPIDR output was 0x0BE11477. This code is described in the reference manual (RM0493) as not being implemented. What is happening?

Hi.For our footprint definition we require a confirmation from you: The letter ‘C’ in the Pin Count ordering information is used for both 48 and 49 pins packages. The WLCSP package is 49 pins.Thanks in advance,Noam  

Hello everyone,I am developing a UI using TouchGFX on a custom board based on the STM32F767. I am encountering visual artifacts during screen updates.As seen in the attached video:In the date selection wheel, the text overlaps, tears, and leaves ghosting artifacts during scrolling.The first menu ("Date & Time", "Language" etc.) is inside a ScrollableContainer with a ListLayout. Initially, the text is corrupted. However, as soon as I scroll this container, the artifacts disappear completely and the screen draws correctly.System Info:MCU: STM32F767GUI: TouchGFX (Version: [Sürüm] )Memory: Framebuffer is located in [SDRAM vb.]Configuration: MPU is ENABLED, D-Cache is ENABLED.What could be causing this issue? Any suggestions on which configurations or settings I should check?Thank you!

After an aborted attempt to get the PSSI interface on the STM32N6 to work with DMA, I have decided to try a different part, the STM32H7A.  Running into a similar problem attempting to get the DMA to work.Here is a snap-shot of what I see:After receiving HAL_OK from HAL_PSSI_Receive_DMA(). I get the error interrupt with an error code of 0.  As may be seen, there is a DMA Transfer error.  This is running on the Nucleo-H7A3ZI-Q board.  The clock tree has been changed to increase the clock speed:The PSSI clock is produced by a PWM Timer and set to a frequency of 10MHz.  Data is from a 12 bit ADC with an active high Ready.  DE is not used.  I have a pull-up on Ready.  With HAL_PSSI_Receive_DMA() in a loop from a frame timer, each call returns HAL_OK followed by the error interrupt.The PSSI setup:The DMA setup:I’ve been studying the examples given on this board for both the H5 and the H7.  Whereas the N6 produced an immediate error response to multiple PSSI DMA attempts, the H7A does not.  T

Hi all,I'm trying to read the DAC output value using the integrated ADC and the connection to it (channel 19). However, I only read random values between [0;2] units. The DAC works properly using the integrated buffer. I route the DAC output to the external pin and to on-chip analog peripherals, so I can confirm the output with a multimeter. The ADC seems to work properly too: I can read internal temperature, VrefInt, and 2 input pins with scan mode. However, when I enable the VDAC_OUT1 and add it to scan mode, I get random values between 0 and 2 (only for VDAC_OUT1, the other readings are fine). Sample times are abondant (few us); I have tried different sampling values, but, as expected, it doesn’t change anything.I configure this setup with the latest version of CubeMX. Readings and DAC configuration are performed using basic HAL (no interrupt and no DMA).Does anyone have an idea to fix this issue?  

Hi everyone, I’m using the X-NUCLEO-IHM08M1 with the g474re core and a BL23E33-01D-04RO motor (which reaches 4000 rpm).I want to use FOC and the motor’s internal encoder, so I’ve made the hardware modifications described in the IHM08M1 manual and those also required by MC Workbench before code generation. I have therefore set the main sensor to the encoder and the auxiliary sensor to the sensorless PLL+observer.In STM32CubeIDE, the motor runs smoothly and the speed is correct, but at low speeds (below 60 rpm) it freezes and sometimes lags... I have no reported firmware errors. I don't have any load connected to the motor (yet).What could be causing this? PID? I can provide screenshots of the signals you want; I’m using CubeMonitor. PWM: 16kHzSW dead time 850nsRegulator execution time: 63us (1 PWM) - three shuntGain: 5.18Bus voltage divider: 19.17Quadrature encoder:average FIFO depth = 16 Input capture filter duration = 0.75 usPID: autocalculate Kp & Ki for both current and speed re

Hi everyone,I'm using an STM32H743 in USB device mode as a virtual USB drive (UF2 protocol) for firmware upgrade. Main program runs in Bank 1 Upgrade firmware is written to Bank 2 During the file copy process (from PC to the virtual UF2 disk), the USB connection drops unexpectedly (host resets the bus, captured by USB analyzer).However, if I connect the device through a USB Hub, the success rate improves dramatically.I understand that in dual-bank Flash architecture, erasing or programming Bank 2 should not interfere with: USB peripheral operation (running from Bank 1) AHB bus access Interrupt latency (if properly configured) But my test shows the opposite: Direct connection → frequent host reset Via Hub → mostly works fine Questions: What could cause the host to reset the bus when only the inactive Bank is being erased/programmed? Why does adding a Hub improve reliability — is it signal integrity, power filtering, or host timing tolerance? Could Flash write/erase temporari

Heyho,H723..H735, using DTCM a lot, also ITCM for some functions.Recently I found some strange behaviour:the global pointer sFlashIntCtl.pu8WrBuf to the buffer u8FlashIntPageBuf (global) is set in function A setting the pointer is working, printf via UART later on function A calls function B pointer sFlashIntCtl.pu8WrBuf is not changed anywhere, no IRQ or anywhere first thing function B is doing: check if pointer sFlashIntCtl.pu8WrBuf != NULL check fails, because sFlashIntCtl.pu8WrBuf = 0 (checked via UART, see below) Here’s the UART output:function A UART output:*** start *** wr SPI flash to APP flash&u8FlashIntPageBuf[0] 20000800sFlashIntCtl.pu8WrBuf 20000800 <- this OKAYsOspiFlashCtl.pu8RdBuf 20000800sFlashIntCtl.u32WrAddr 08040000sFlashIntCtl.u32ChkAddr 08040000sOspiFlashCtl.u32RdAddr 00000100sOspiFlashCtl.u32RdLen 32...function A calls function Bfunction B UART output:#E FlashIntWrPage(): pu8WrBuf = NULLsFlashIntCtl.pu8WrBuf 00000000 <- WTF ?&u8FlashI

Hi everyone,I am working on an STM32H745 dual-core device.My current setup is:CM7 starts first after reset (default hardware behavior). CM7 performs minimal initialization and releases CM4. The bootloader runs on CM4. CM4 bootloader is located at 0x08100000. CM4 application is located at 0x08120000.The CM4 bootloader validates the application image and then jumps to the CM4 application using the standard vector table jump sequence.My goal is to support firmware updates of the CM4 application while the bootloader itself is running on CM4.I would like to understand the recommended architecture and any limitations for this scenario:What is the recommended way to organize flash banks when the CM4 bootloader needs to update the CM4 application? Is it safe for a CM4 bootloader executing from Bank 2 to erase/program another region in the same bank where the CM4 application resides? Should the bootloader be moved to a different flash bank or SRAM during the update process? Are there any STM32H

Hi, I have a custom board with a STM32WB55RG and I’m trying to upgrade the Wireless stack (and the FUS firmware). When I perform a Read FUS Infos in STM32CubeProgrammer, it returns v0.0.0 value for the FUS Version (I know that it should be v1.2.0 as it used to be v1.2.0). If I read the memory at address 0x20030000 I have the following value:  where DeviceInfoTable seems valid,  the Wireless stack version is1.15.0 build 3 and FUS version is 1.2.0 SFSA value is 0xce (address: 0x080ce000) Any ideas why I see this value (v0.0.0) when I read the FUS infos? Moreover, when I try to update the wireless stack (or the FUS firmware), everything looks to go well but when I read back the FUS infos they are still the old values. 

Hi,Any reason why the GBW of the OPAMP is having such a wide tolerance? Is it purely because the values are best-worst case design calculations?In comparison, the Gx and Fx variants has better limits.

Hi everyone!I have a project where I start, with the help of the Timer 3, three ADCs(ADC1, ADC2 and ADC4). Each of them samples 256 samples and then stops. Then I disable them and start a calibration process on all three ADCs.This is repeated with a frequency of 4Hz approx. Interesting thing is that after calibration I get very often different calibration values for ADC1, not really often for ADC2 and rarely for ADC4. Like this:60, 61, 6260, 61, 6261, 61, 6260, 61, 6260, 60, 6261, 61, 6261, 61, 6260, 61, 6260, 61, 62...Calibration is done with HAL function from ST. ADCs are turned of during calibration (ADEN = 0). Vref is external(3v) and it is stable, but I believe that offset calculation during calibration does not really use Vref voltage. Or it does?So I’m a bit confused. Is here some ADC guru of Yoda level?I appreciate any help.

Hello ST team,I am using a P-NUCLEO-LRWAN3 starter kit with the NUCLEO-F746ZG gateway board.I accidentally overwrote the original gateway firmware on the F746ZG. I have already recovered the board so that it can be connected and programmed again with STM32CubeProgrammer, but I no longer have the original gateway firmware binary.I tried flashing another gateway binary:st-nucleo-lora-gw-at-fw-v2.1.7-eu868-TTN.binThe firmware runs, but it is clearly not the correct one for my hardware. After flashing it, the serial output shows EU868 / TTN settings and reports:router.eu.thethings.networkuplink/downlink port 1700channels around 867–868 MHzERROR: Radio A frequency and type are not matchedERROR: Radio B frequency and type are not matchedBefore I overwrote the original firmware, the gateway output was different. The original serial output showed:VERSION: 2.1.7, Nov 6 2018LORAWAN SERVER: ap1.loriot.iouplink/downlink port 1780channels from 471500000 to 472900000So I believe the original firmwar

Hello,I’m facing a strnge issue in the code generated by CubeMX for the STM32L496ZG.The project was imported in CubeIDE and compiled fine.but, as soon as HASH is activated the project no longer compiles and throws several hundreds of errors.CubeMX version is 6.17.0CubeIDE version is 2.1.1Looking at the errors, it appears that the HASH symbol is not defined, resulting in the associated code being grayed out.Regards

I have 2 problem in my touchgfx project.I use STM32G4 series. I have an external loader with a starting address of 0xA0000000. I can perform read and write operations with this loader using CubeProgrammer. However, when I define the external loader via CubeIDE, it programs the address 0x080000000. Then I get Hard Fault.   Here is my flash.ld The external loader starts working when I start it with the external loader address 0x00000000, but I want to start with 0xA0000000. How can i fix it ?Also my second problem is texts. My text datas are sending to external flash, but it is not appear. Then I changed font section to internal flash in flash.ld, my text was appear. Here is my changed sections side.  The textures are changing because something else is changing. Why isn't the screen showing the text I added with the external loader?

I am working on an STM32 based robot controller using an STM32F4 series board. The system includes IMU, encoders, and multiple sensor modules. During vibration and movement, some jumper connections become unreliable. I am currently using standard Dupont wires for prototyping. However, repeated disconnects are causing unstable sensor readings. I want to move to more robust connector solutions for PCB to wire interfaces.I am confused about which connector types are best for pin based headers. Should I use JST, Molex, or locking header connectors instead of Dupont? What connector systems are commonly used in STM32 embedded designs?I also need something suitable for frequent assembly and maintenance.

Hello guys,recently in my lab a new batch of STM32F401RET6U MCUs on Nucleo-64 boards is arrived (MB1136-F401RE-C04 SN K252502xxx). After I set these in the same hardware way of my old ones (i switch UART2 PINs PA2 (TX) and PA3 (RX) from the ST-LINK to the ST Morpho connectors desoldering SB13 and SB14 and soldering a 0Ohm on SB62 and SB63), and uploading a version of my firmware which today is still working properly on my old boards (MB1136-F401RE-C04 SN A204505xxx), it doesn’t run correctly for  the new ones. The main problem i notice in debug mode is that UART1 and UART2 sometimes work correctly and sometimes not (confirming also my hardware modifications when the lines are ok), while SPI2 which I use to communicate with the ethernet chip W5500 on my carrier board never works (even drastically lowering its frequency, and with the old boards it works at 21MHz), I2C1 line always seems to work properly. Being more precise, in order to mount all Nucleo-64 boards on my carrier board I’m f

hi~!  I made a IOT prototype with STM32U031K8T6, but I can't download firmware. The connection isn't working ad it should, can anyone tell me the issues with the attacked circuit ?? I've tried both j-link and st-link download tools.    please reply from users who have used STM32U031.   

I have an external loader with a starting address of 0xA0000000. I can perform read and write operations with this loader using CubeProgrammer. However, when I define the external loader via CubeIDE, it programs the address 0x080000000.  Here is my flash.ld The external loader starts working when I start it with the external loader address 0x00000000, but I want to start with 0xA0000000. How can I fix it ?

Hello everyone,I am currently working with an STM32G4 series MCU using multiple FDCAN peripherals and would like to hear about other developers' experiences regarding CAN communication reliability and synchronization.In projects where both FDCAN1 and FDCAN2 are active, have you encountered any challenges related to:Clock configuration and synchronization Bit timing calculations Bus load handling Message filtering across multiple instances Error recovery and bus-off situationsI'm particularly interested in best practices for configuring multiple FDCAN instances to ensure stable communication in automotive and industrial applications.Any recommendations, examples, or lessons learned from real-world deployments would be greatly appreciated.Thank you in advance for sharing your experience