⁠STM32F446 SPI Slave DMA Timeout when Interfacing with Xilinx ZCU104 FPGA Master

[Kevindied]

Hello ST Community,

I am currently working on a hardware integration project where a Xilinx ZCU104 FPGA acts as the SPI Master, and an STM32F446RE acts as the SPI Slave. We are attempting to establish a stable full-duplex SPI communication using DMA, but we are consistently encountering a "Communication Timeout" on the Master side, and the STM32 RxBuffer remains empty (all zeros).

Here are the implementation details and the troubleshooting steps we have already verified:

### 1. Configuration & Code Snippet
* Data Size: 8-bit SPI data size, but grouped into 4-byte (32-bit) transfers to match the FPGA's 32-bit register data width.
* STM32 SPI Configuration: Slave Mode, 2 Lines Full-Duplex, CPOL=0, CPHA=0 (Mode 0), MSB First.
* NSS Management: Hardware NSS Input (SPI_NSS_HARD_INPUT) on PB12.
* DMA Configuration: DMA1 Stream 3 (RX) and Stream 4 (TX) enabled with circular or normal transfer.

In `main.c`, we initialize the peripheral and start the listening process as follows:
```c
#define BUFFER_SIZE 4
uint8_t TxBuffer[BUFFER_SIZE] = {0x11, 0x22, 0x33, 0x44};
uint8_t RxBuffer[BUFFER_SIZE] = {0};

// Inside main() after peripheral initialization
HAL_SPI_TransmitReceive_DMA(&hspi2, TxBuffer, RxBuffer, BUFFER_SIZE);
 

[Saket_Om]

Hello ​@Kevindied 

For reliable SPI communication, the slave device should be prepared to receive and transmit data before the master begins generating the clock signal.

[Kevindied]

Thank you for your valuable insight! Yes, we have strictly followed this sequence. The STM32 (Slave) is always powered on and calls `HAL_SPI_TransmitReceive_DMA` to enter the listening state well before the FPGA Master triggers the Python script to generate the clock.

However, we suspect that the default AXI SPI clock from the FPGA might be too fast for the STM32 to sync properly at the very first falling edge of the NSS line. Given the APB peripheral clock constraints on the STM32F446, what would be the maximum recommended SCK frequency for the Slave to achieve reliable latching without missing the initial clock pulses?

[Saket_Om]

Hello ​@Kevindied 

The maximum reliable SPI SCK frequency in slave mode is approximately Fpclk/2 for 8‑bit data size in this configuration.

 

[Andrew Neil]

​@Kevindied 

```c

Note that this forum doesn’t support markdown - please see: 

 

[Kevindied]

ok,thank you very much.

[MGogr.1]

Have you tried using separately?

HAL_SPI_Transmit_DMA(hspi, pData, Size);
HAL_SPI_Receive_DMA(hspi, pData, Size);

 

[Kevindied]

Thanks for your recommendation! I will test this approach later and report back with the results.