STM32 MCUs

On STM32H733, the HAL provides __HAL_DBGMCU_FREEZE_FDCAN() in stm32h7xx_hal.h but it is conditionally compiled:#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)#define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))#endifDBGMCU_APB1HFZ1_DBG_FDCAN is not defined in stm32h733xx.h, so the macro does not exist at compile time and calling it gives:error: implicit declaration of function '__HAL_DBGMCU_FREEZE_FDCAN'Questions:Is FDCAN freeze during debug halt supported on STM32H733? If yes, why is DBGMCU_APB1HFZ1_DBG_FDCAN missing from stm32h733xx.h — is this a bug in the device header? What is the correct bit position to use as a workaround via direct register write? I need to pause the FDCAN peripheral during debugging, that is my goal. Thanks you very much for helping me out. 

I am developing an application on NUCLEO-N657X0-Q using Getting started image classification as base code. I need to add to the project the standby mode and right now when it enters standby mode, then it fails to resume correctly, i guess because part of the application is lost when system wakes up (retention is only 80 KB).The total size of the application is much bigger then 80KB and I am not sure how to extend the actual retention memory in use adding the TCM retention memories.Actually the application code is placed at 0x34000400.Is there an example on how to place the application also in TCM? I thought that another solution could be placing in retention at 0x34000000 the fsbl code and maybe in axisram2 the application, so that when the system wakes up after a standby it executes again fsbl and gets from external flash the application code.I tried this last part changing the linker files, setting 0x34000000 for fsbl and 0x34100400 for application, then in fsbl code i set address 0x

I wanna implement Master and Slave ethercat protocol on stm32h7 series. Is there any examples available on subject?. Where should i start. Any resources?

HiI am implemented flash write protect on STM32U5 using option byte register FLASH_WRP2AR.Following these steps to write protect page 0x4C and 0x4D page in Bank 2- Unlock flash - Unlock Flash option register(FLASH_OPTR)- Unlock flash page by setting UNLOCK bit(31) in FLASH_WRP2AR- Write WRP2A_PSTRT[6:0] of  FLASH_WRP2AR with value 0x4C- Write WRP2A_PEND[[6:0] of  FLASH_WRP2AR with value 0x4D- Lock flash page by clearing UNLOCK bit(31) in FLASH_WRP2AR - Initiate option byte programming by setting OPTSTRT bit FLASH_NSCR register - Wait for flash operation to complete - Lock FLASH_OPTR register - Lock FlashThis sequence works some times , however most of the time  after option byte programming FLASH_WRP2AR value resets to following value and write protect is disabled. - WRP2A_PSTRT[6:0]: 0x7F - WRP2A_PEND[[6:0]: 0x00OPTWERR bit sets in FLASH_NSSR indicating that invalid configuration, however configuration looks right.Regards,Hareesha 

I need to use embedded STM32H573 bootloader to update customer application using UART1 or uart3.I try to use AN2606, but no success. May you provide correct code to jump from application to the embedded bootloader for specific processor model: STM32H573, please?

I am a user of the NUCLEO-N657X0-Q board. I am using the NUCLEO-N657X0-Q board with Root of Trust enabled, and I want to use the RTC.Out of the 3 stages  (FSBL → Secure App → Non-Secure App)  I want to use the RTC in the Non-Secure App. My development environment is as follows:1> Development tool: Keil uVision V5.422> Example source: STM32Cube\Repository\STM32Cube_FW_N6_V1.2.0\Projects\NUCLEO-N657X0-Q\Applications\ROT\OEMuROT_Appli3> Development board: NUCLEO-N657X0-Q The biggest problem is that when HAL_RTC_Init() is called in the Non-Secure App, it hangs. The source for STM32Cube_FW_N6_V1.2.0\Projects\NUCLEO-N657X0-Q\Applications\ROT\OEMuROT_Appli was created by referencing STM32Cube_FW_N6_V1.2.0\Projects\STM32N6570-DK\Applications\ROT\OEMuROT_Appli. The code I added is as follows.1. Added to the main function of the Secure App.HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RCC_PERIPH_INDEX_RTC, RIF_ATTRIBUTE_NSEC);2. Added a function to the Non-Secure App.RTC_HandleTypeDef RtcHa

Most of the default settings on the ST workbench for the Charge Boot Capacitor Time are 10ms. However, with the B-G431B-ESC1 Discovery kit with STM32G431CB MCU, calculations show that the charging time for a 1-microfarad capacitor should not exceed 10 microseconds. So why is the default setting 10ms?

Starting with the http server example i inserted LwIP SNTP and RTC based on medium-high LSE and smooth calibration with a PI controller. After some hours of SNTP comparisons every 120 seconds the calibrator settles at -12.3 units. My firmware implements fractional calibration by tracking remainders. The running average over 10 consecutive time comparisons exhibits < 1 msec rms. A nice result.Then i modified predivider setup from standard 127/255 to 31/1023 in order to improve resulation. After a backup domain reset the new setup works and delivers consistent time comparisons. I also unsoldered R11 in order to separate PC13 from the “SD card present” switch in order to look at the RTC calibration output.The calibration output shows 4 Hz instead of 1 Hz. I may try an RTC alarm to get the 1 second output pulse. The smooth calibration feature no longer works as expected. Apparently the mapping between CALR register settings and what the circuit really does no longer follows the referenc

Hi! I use LL drivers to work with UART as follows: LL_USART_SetRxTimeout(USART1, 3 * 11); LL_USART_EnableRxTimeout(USART1); LL_USART_ClearFlag_RTO(USART1); LL_USART_EnableIT_RTO(USART1); LL_USART_EnableIT_RXNE(USART1);and it works fine until I switch the MK to STOP1 mode  HAL_SuspendTick(); HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); // STOP1 HAL_ResumeTick();What do I need to do to get this to work in STOP1 mode?

Hi, Can I use DAC of STM32L476RCTX for audio application. I have to give output of DAC to MAX97220(Audio amplifier IC). Frequency range of audio is 10Hz to 20kHz. Can you please suggest any application note for this. Audio files will be fetched from SD card with SPI interface.Can you please suggest any code example or library that is already available for this type of example.  Regards,Anurag 

I have added a wolfSSH ICube repo to my project. It does not compile, showing:  Cube/Middlewares/Third_Party/wolfSSL_wolfSSH_wolfSSH/wolfssh/src/internal.c: In function 'GenerateKey':Cube/Middlewares/Third_Party/wolfSSL_wolfSSH_wolfSSH/wolfssh/src/internal.c:2215:15: error: implicit declaration of function 'wc_SSH_KDF'; did you mean 'wc_HKDF'? [-Wimplicit-function-declaration] 2215 | ret = wc_SSH_KDF(hashId, keyId, key, keySz,I checked the configwolfSSL.I-CUBE-wolfSSL_conf.hand it seems to be missing the wolf repo has:/* Enable wolfSSL features needed for wolfSSH */#define WOLFSSL_WOLFSSH           /* Enable wc_SSH_KDF function */  Do I have to manually add it? Am I missing some other config that enables it?wolfSSH example referencewolfip/src/port/stm32h563/user_settings.h at master · wolfSSL/wolfip 

Hi,I modified the BLE_HeartRate example for Nucleo-WBA25CE1 by adding another channel - IN8 - to read the voltage of a solar panel. The input is between 0V and 3V because i use the divider. In CubeMX I added an additional channel IN8 and generated the code. In the code I define the handle for ADCCTRL:ADCCTRL_Handle_t LLVoltageRequest_Handle ={ .Uid = 0x00, .State = ADCCTRL_HANDLE_NOT_REG, .InitConf = { .ConvParams = { .TriggerFrequencyMode = LL_ADC_TRIGGER_FREQ_LOW, .Resolution = LL_ADC_RESOLUTION_12B, .DataAlign = LL_ADC_DATA_ALIGN_RIGHT, .TriggerStart = LL_ADC_REG_TRIG_SOFTWARE, .TriggerEdge = LL_ADC_REG_TRIG_EXT_RISING, .ConversionMode = LL_ADC_REG_CONV_SINGLE, .DmaTransfer = LL_ADC_REG_DMA_TRANSFER_NONE, .Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN, .SamplingTimeCommon1 = LL_ADC_SAMPLINGTIME_814CYCLES_5, .SamplingTimeCommon2 = LL_ADC_SAMPLINGTIME_1CYCLE_5 }, .SeqParams = { .Setup = LL_ADC_REG_SEQ_CONFIGURABLE,

I am working on STM32H745BIT6 (dual-core: Cortex-M7 + Cortex-M4).Issue:DMA is functioning correctly when used from the CM7 core The same DMA configuration does NOT work when executed from the CM4 core

I am using a stm32h562agi6 and configured fdcan2. It works!But then I wanted to create a zephyr os project and saw that there the fdcan2 is not available for stm32h562xx in general. I did some investigations and also the datasheet actually states that fdcan2 is not available (features and peripheral counts). I basically read everywhere that it has only one fdcan peripheral. I use PB5 and PB6 which are only listed for FDCAN2.  So what is true now? Is it because it’s a UFBGA169?

Hi everyone I have a bit trouble initializing the JPEG peripheral on the N6. See the stack trace:  I feel like this has something to do with the RIF? I don’t know, this chip is very new to me. If anyone can help me, it’d be greatly appreciated. Best regards

Device A is an Ethernet implementation based on the STM32F107VCT6 microcontroller and the LAN9303 Ethernet transceiver. It connects to a host computer via a Layer 3 switch, with Device A and the host computer assigned IP addresses in different network segments.Two batches of STM32F107VCT6 microcontrollers are currently deployed. With the Layer 3 switch properly configured, the following test results are observed:For the older batch of STM32F107VCT6 devices, the host computer can successfully ping Device A, regardless of whether the Layer 3 switch is a Huawei or TP-LINK model. For the newer batch of STM32F107VCT6 devices, the host computer cannot ping Device A when using a Huawei Layer 3 switch; however, ping communication is successful when using a TP-LINK Layer 3 switch.The above observations indicate a batch-specific anomaly in the network functionality of the STM32F107VCT6. What is the specific root cause of this issue?Upon verification, the defective STM32F107VCT6 units have lot co

Hi,I am working with an STM32H7 microcontroller and the EVB-LAN9252-SPI board from Microchip Technology.I would like to establish communication between the STM32H7 MCU and the LAN9252 over the SPI interface. Could you please provide guidance on the hardware interfacing, software setup, and initialization procedure required to bring up the communication?Additionally, please let me know the software packages, drivers, middleware, or example projects that would be needed for this implementation.

I'm using an STM32H7S78-DK board and I have a part of the firmware that, from the boot, updates the FLASH from a .bin inside an SD cardThe code is pretty simple as I loop the FLASH comparing every sector with the one in the SD card and, if different I erase the internal flash sector and write the new one.Everything was working correctly until a update the code via CubeMXThe read seems to still workingif (EXTMEM_Read(0, fw_offset, flash_buf, br) != 0)but as soon as I do theif (EXTMEM_EraseSector(0, fw_offset, FLASH_SECTOR_SIZE) != 0)I got an errorThe crash happens in if (EXTMEM_DRIVER_NOR_SFDP_OK != EXTMEM_DRIVER_NOR_SFDP_SectorErase(&extmem_list_config[MemId].NorSfdpObject, local_address, sector_type)) { retr = EXTMEM_ERROR_DRIVER; }I've rolled back just the driver in the STM32_ExtMem_Manager, and everything started working againI've noticed that quite a few files have been changed, including the addition of #define EXTMEM_DRIVER_CUSTOM     0In the conf_temp

I am currently working with SBSFU on the STM32H743ZIT6 series and have implemented several modifications to its core functionality. I would like to clarify the potential impact of these changes.1. Modification to SBSFU FunctionalityI have altered the default SBSFU behavior by replacing the traditional firmware swapping mechanism with a bank-switching approach to reduce application downtime.Both Bank 1 and Bank 2 will contain the bootloader and the application. Bank selection is managed using the swap option byte.2. Relocation of Swap AreaI plan to relocate the swap area from Sector 8 to Sector 15, considering that Bank 2 spans from Sector 0 to Sector 7.The swap area is used during the decryption process. It requires 128 KB of memory.3. Clarification RequiredI would like to understand whether these modifications will have any impact on the system:Will the transition from a swap-based mechanism to a bank-switching approach affect the core functionality, integrity, or reliability of SBSFU

In the reference manual RM0440 Rev9 of STM32G4 family the bit combination 0b000 for the BLANKSEL setting in the comparator registers COMP_CxCSR is not documented: (Screenshot of page 771 and 773)I assume 0b000 means blanking input disabled, but it should be written in the rm.

When will the NUCLEO-C5A3ZG  be available via distributors?The st.com site lists it as available(mass production), but none of the distributors has listed it at all. And the estore lists it as coming soon. Do you have any more concrete dates, will it be available anytime soon?   Best

Hello,I’m working on a design using the STM32H750IBTx (LQFP176) running at 400 MHz with FreeRTOS, and I’ve encountered a strange intermittent issue with the display that only appears after long periods of operation.Problem Description:After about 30–40 days of continuous operation, the display starts to flicker and glitch.Once the flicker begins, it persists continuously for around 24 hours and then self-corrects without reboot.Performing a power cycle or reset also immediately clears the issue.No other functional failure is observed (system remains responsive, logs continue, etc.)System Overview:Display: 800×480 RGB LCD connected via LTDC interface (RGB565 format)SDRAM: 32 MB IS42S16160J-6TLI, 8192 rowsQSPI: 64 MB MX25L51245GConnected via FMCFMC clock: 200 MHz, SDRAM clock: 100 MHz (FMC clock divided by 2)Refresh rate: Configured for standard 64 ms / 8192 = ~7.8 µsREFRESH_COUNT and other parameters are set as below#define REFRESH_COUNT ((uint32_t)1539) /* SDRAM refresh counter 200MHz

STM32N6570-DK: BOOT0/BOOT1 switches appear to have no effect. In DEV boot (BOOT1=H), external loader MX66UW1G45G_STM32N6570-DK fails with "Init function fail with timeout" via both STM32CubeProgrammer 2.22.0 CLI/GUI and STM32CubeIDE (ST-LINK FW V3J17M10, hot plug and under-reset modes, AP1). In serial boot (BOOT0=H), no USB DFU enumeration on USB1 and no UART acknowledgement on the STLink VCP (115200 8E1). SWD debug access works normally; the board previously booted user firmware from flash. Official STM32N6-OOB readme procedure reproducibly fails at the first sector erase.

Good afternoon,I am working with the STSW-TTM005 example for a resolver-equipped motor and encountered an issue:Link: STSW-TTM005 | Product - STMicroelectronicsThe motor does not rotate, but instead oscillates between windings.In sensorless mode, the motor rotates correctly.During debugging, the resolver angle appears correct.I tried changing that setting:#define RESOLVER_ANGLE_OFFSET_DEGREE 185.0f // Angular offset in electrical degrees between the resolver and the rotor's magnetic flux, but it didn't workCould you please clarify which resolver-equipped motor was used to validate this solution? My setup is as follows:Control board: NUCLEO-G431RBDriver board: based on DRV8353Resolver board: STEVAL-TTM005AFirmware version: 5.4.8Motor specifications: PMSM with resolver, 20 poles, 24V DC, 67A peakI would appreciate guidance on whether my configuration is compatible and any recommended adjustments.Thank you for your support.Best regards, Anatoliy

Hello.I am building a Thread SED product using the STM32W5MMG. Recently, after upgrading the firmware version to v1.24.0, I encountered a problem with low-power startup.Upon investigation, I discovered that the location of the “Init_Debug();” call within the MX_APPE_Init() method in app_entry.c was different.Previously (in v1.23.0), I had written the following code within the /* USER CODE BEGIN APPE_Init_1 */ block, and this worked correctly. HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer *//* USER CODE BEGIN APPE_Init_1 */#if (CFG_FULL_LOW_POWER != 1) Init_Debug();#endif UTIL_LPM_SetStopMode(1 << CFG_LPM_APP, UTIL_LPM_DISABLE); UTIL_LPM_SetOffMode(1 << CFG_LPM_APP, UTIL_LPM_DISABLE); Led_Init(); Button_Init();/* USER CODE END APPE_Init_1 */  However, with the transition to v1.24.0, the call location of Init_Debug(); was changed as follows. HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */ Init_Debug();