STM32F4 I2C CR2 Peripheral clock frequency

[LGrüb.1]

Dear Forum,

I'm using a STM32F401 and implemented the I2C as Target transmitter (Slave) answering a I2C question. 

I'm programming the I2C CR2 (FREQ Bits) Register as follows with correct speed (42 MHz)

I2C1->CR2 = ((DRV_RCC_GetPCLK1Freq() / 1000000u) & I2C_CR2_FREQ_Msk);

 I've noticed some spikes when the STM32 I2C controller generates the answer, see below (yellow markings)

Blue: Clock generated by the controller (the clock speed is about 200kHz)

Red: Adrdess Byte generated by the controller, Data Bytes generate by STM32 I2C transmitter (answer) with spikes

When the FREQ Bits of I2C_CR2 Register are zero, this spikes doesn't occur, see below

The Reference Manual RM0368 Rev 6 for the I2C CR2 writes:

It is noticed that this FREQ bits must be configured to generate I2C compliant Signals. Anyhow from EMC perspective this spikes are bad because the radiate a wide spectrum. I've found nowhere information of correct I2C specifiation/behaviour of the Data Signal the be compliant, anyhow the data is transfered correctly to the controller.

Q: must the FREQ bit of CR2 be set in slave mode?

Q: what is I2C compliant behaviour

Q: How about CCR Register, is it neccessary to set in slave mode (how to set the I2C_CCR_FS Flag)?

Q: Is this Standard or Fast Mode (because of 200 kHz clock)?

Q: TRISE Register doen't show any influence if this case, is it of any concern?

 

Thank you for your thoughts and time.

regards,

Lorenz

[FBL]

Hi ​@LGrüb.1 

A1/ CR2.FREQ is not only for master mode. On this peripheral, it is used by the hardware to derive internal timing thresholds and to make the signal behavior compliant with I2C requirements.

A2/ The controller must comply with : data setup time, data hold time, SDA valid around SCL edges, SCL timing, rise /fall time.

A3/ No, not for clock generation. In slave mode, the master provides SCL. So, CCR is a master timing register. FS means Fast Mode in master mode. In your case, slave mode, not relevant.

A4/ 200 kHz bus clock should Fast Mode.

Can you check bus capacitance, PCB routing ? Check if spikes are real or measurements artifact. If it appears on SDA only when the slave is transmitting, the artifact likely concerns SDA transitions not SCL generation.