STM32 MCUs

Hi,I am using an STM32N655X0H3Q interfaced with an NHD-7.0-800480EF-ASXN#-CTP display that uses the FT5426G capacitive touch controller. I have created a TouchGFX screen containing a single button widget. No interactions are currently assigned to the button (I had previously tested it with a screen-change interaction, but the behaviour remained the same, so I removed all interactions and am now testing with only the button widget present on the screen).The touch controller appears to work correctly otherwise. I can continuously poll touch events inside STM32TouchController::sampleTouch() and successfully print the touch coordinates and number of touch points when touching any area of the screen outside the button.However, as soon as I touch the button widget, the application hangs. The button disappears and the display turns into a plain screen. At the same time, the continuous polling inside STM32TouchController::sampleTouch() stops completely, indicating that TouchGFX is no longer ca

Have successfully worked throughSTM32Cube_FW_U5_V1.8.0/Projects/B-U585I-IOT02A/Applications/SBSFU/readme.htmlI need to port this (..boot, ..loader, ..appli) to a custom board running STM32U585VIT6.Within the readme it states "This example has been tested with STMicroelectronics B-U585I-IOT02A board and can be easily tailored to any other supported device and development board."Is there an example / idiots guide to work through doing the above?Thanks 

我尝试使用 STM32L4R9 与 AD7768 通信，使用 8 个通道。我想知道的是：是否可以使用 DCMI 建立 AD7768 与微控制器之间的通信（微控制器支持，但我不确定 AD7768 是否支持 DCMI。）如果 AD7768 也支持，我想知道 PCB 应该如何正确布线。Translation to English I am trying to communicate with the AD7768 using the STM32L4R9, using 8 channels. What I want to know is: is it possible to use DCMI to establish communication between the AD7768 and the microcontroller (the microcontroller supports it, but I'm not sure if the AD7768 supports DCMI.) If the AD7768 supports it as well, I would like to know how the PCB should be wired correctly.

Hi community, I have been facing some instability in transmission of the UART in STM32 LQ5CGU6P, When we measure the TX and RX line when it fails to transfer the data, both TX and RX are low, is this ever experienced before? help us out to troubleshoot this, has anyone come across this kind of scenario with UART before?

Hello,I'm currently integrating the SBSFU 2.8 for one of our board, that use a STM32H753, with a dual-slot configuration.I'm adapting the example for the STM32H753ZI. For now, this mostly involves modifying the USART (use the 6 instead of the 3).I am currently trying to set up the system to resume operation after a power outage. I defined ENABLE_IMAGE_STATE_HANDLING in the projects SeCoreBin and SBSFU.This is my scenario:Download of a UserAppValidation of the downloaded UserAppDecryption of the UserAppStart of the swap between the DownloadSlot and the ActiveSlot/!\ Power outage!Power returnResume of the installation processCurrently, the resume always fails when checking the trailer (in CheckTrailerMagic).I checked what he wrote as trailer (in WriteTrailerHeader), and what is written is indeed what is read after the reset.What's strange is how he slices up what he's checking.If we look at the names of the arrays in the CheckTrailerMagic function, we have:FieldValue readm

Hello,I’m working with the STM32CubeWB package and trying to understand ST’s plans regarding VEX documentation following annoucements here https://wiki.st.com/stm32mcu/wiki/Security%3ASTM32%20Software%20security%20policies%20Q%26A# Could you clarify the plan for STM32CubeWB specifically?Is VEX publication still planned for STM32CubeWB? If yes, is there an estimated timeline or target STM32CubeWB release version? Where will the VEX files be published: inside the STM32CubeWB package, on st.com, on GitHub, or next to the existing sbom_cdx.json file? Will VEX documents be provided per STM32CubeWB version, or only for the latest available package? Will VEX entries map directly to SBOM components using bom-ref or Black Duck component IDs from the associated SBOM, or another identifier? Can we expect more detailed vulnerability information than what is currently available through PSIRT bulletins, for example affected/not affected status, justification, fixed version, remediation, or workaroun

Hi, I face the problem with the touchgfx frame rate render has drop periodic after 1000ms that make the animation image (wait circle) has choppiness.My project run on custom STM32U5 has 3MB RAM and 4MB FLASH (I don’t use the external memory). The LTDC configuration at 60Hz(24.5Mhz) for screen 800x480 resolution. The signal when screen not update(full)The signal when screen not update(full)The signal when screen not update(zoom in to see the VSYNC signal)The signal when screen not update(zoom in to see the VSYNC signal) The signal when screen animation the imageThe signal when screen animation the imageThe VSYNC signal is perfect at all.You can run the LogicSystemTimingAnalysis.html in .zip then load the .csv file to see the signal. Thanks,Phat 

Hi, Is there a way to disable Boot0 on PA11 on STM32WL33 ? I can’t find any Bytes Option. The only thing I can find, is we can re map PA11 to another pin.Thanks

I have 3 physical buttons: next, enter and previous. After next or previous clicked I have to move the frame which select the flex button on the screen. When I clicked the enter button selected button on the screen should be pressed and released. I mean the selected button should do what I set in TouchGFX Designer. How to simulate the real pressing on touch screen using physical button ? Also I have a container including the keyboard with the flex button. I would like to use the same approach.

Hi all,I am bringing up an ISSI IS66WVO8M8DBLL OctalSPI PSRAM (OctaRAM) on an STM32H563VIT6 overOCTOSPI1 in memory-mapped mode (window at 0x90000000). Reads, register access, and"write a location then read it back immediately" all work perfectly. But any SUSTAINEDor SCATTERED write workload corrupts data: rows that are not continuously re-writtenlose their contents within a few seconds, and some writes come back wrong.This matches errata ES0565 section 2.5.12 ("Variable latency is not supported when arefresh collision occurs during a write access to some OctaRAM memories"). I applied thedocumented workaround - forcing FIXED latency in the memory's configuration register -and I run in the documented MTYP=0b011 (Macronix OctaRAM) mode. The corruption persists,byte-for-byte identical, with the workaround correctly applied and verified by read-back.I have reproduced this on TWO separate boards with identical results, so it is not asingle bad device.Has anyone got OCTOSPI memory-mapped WRIT

Hi everyone,I am using an EVSPIN32F06Q1S1 board to drive a turbomolecular pump motor. Since the exact motor was not available in Motor Control Workbench, I imported a different motor and manually updated the parameters.The project was generated using MCSDK with FOC + Sensorless Observer (STO+PLL) and flashed successfully. Motor Pilot connects correctly, and VBUS is reported as approximately 316 VDC with a 220 VAC input.However, when I press Start in Motor Pilot, the motor does not start and I receive:MotorControlProtocol: ASPEP_RESP ERROR: CMD_NOKThe state eventually changes to FAULT_NOW, but no detailed fault information is shown. Motor Pilot also reports several register access warnings such as:Accessing register [...] resulted in error[5]although communication with the board remains active.At present, no motor is connected to the inverter. We are trying to verify the controller operation before connecting the actual turbomolecular pump.My questions are:Is it expected for an MCSDK se

 Hello,I have inherited some code where a 5kHz 50% PWM is output in center aligned mode using TIM1. CK_PSC is 275MHz, CK_CNT is 137.5MHz (I think) because PSC = 1.The pattern output matches the implementation:  The yellow trace is a GPIO pin that is toggled in the ISR HAL_TIM_PeriodElapsedCallback(). I want to to keep the same 50% duty but half the frequency to 2.5kHz using the prescaler.From the TRM, it seems I just have to modify PSC from 1 to 2. However, when I do this by poking the SFR register using the debugger, I get the following output:  As you can see, the PWM ratio changes but the frequency does not. I’m at a loss to understand why. So would be grateful for any suggestions.Thank you. In case it helps, here’s my register dump. I have no idea what DMAR is that is my next step.  

Hi, Could you please explain the proper command sequence for smoothly transitioning a motor from Forward to Reverse operation?Currently, my sequence is:STOP → DIR → SET_SPEEDThis assumes the STOP command was issued while the motor was already in the RUNNING state. However, with this sequence, the motor will not reverse direction. The only sequence that consistently works is:STOP → DIR → START → SET_SPEEDWhile this does reverse the motor, I'm running into another issue: every time I issue a START command (this applies at any given point in time), the motor immediately accelerates to approximately 2000 RPM before settling. After that, SET_SPEED commands work as expected.Is there a recommended sequence for changing direction, or is there something I may be overlooking in my implementation?Any input would be greatly appreciated.Thanks. 

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I am currently using the NUCLEO-H7S3L8 CN2 Type-C port as a USB_OTG_HS embedded PHY host/source.The TCPP03 source path opens successfully, and both the USB stick attachment and port reset are working. After the reset, HPRT reads 0x00001005, which seems to indicate speed=HS and that the port is enabled.However, during the first EP0 SETUP GET_DESCRIPTOR request: HAL_HCD_HC_SubmitRequest() = HAL_OK HAINT = 0x00000001 HCINT = 0x00000080 TXERR = 1 xfer_count = 0 The exact same issue occurs even during a raw HAL EP0 smoke test, prior to involving USBX/FileX.I would like to verify the following points: What is the mandatory clock/power initialization sequence when using the USB_OTG_HS embedded PHY host on the H7S3L8? Is it acceptable to use HSI → PLL3Q for the USBPHYC clock, or is an HSE strictly required? What are the necessary settle/wait conditions after enabling USBHSREG? Are there any required CC/UCPD configurations for the CN2 Type-C/TCPP03 source setup, apart from the PM9

I am working on a project to drive a door using a PMSM motor in position control mode. I am trying to add an emergency brake function. In an emergency, when the operator pushes a button, motor should brake and then return to its starting position without harming anyone.I know there is PWMC_TurnOnLowSides() function (https://community.st.com/t5/stm32-mcus-motor-control/how-can-i-stop-the-motor-urgently/m-p/597309#M8287 ). But it is just stopping the motor, not braking. I have tried this function.As far as I know, there is no such API in position control mode.If I am wrong, is there an API to brake the motor in an emergency? Can anyone help me? Do you have any advice for me?Any information you provide will be welcomed.   Project:ST MCW Ver             : 6.3.2STM32CubeIDE Ver : 1.18.1Driving algorithm      : FOCControl board            : Nucleo-G474REPower board        &

Hello Team,I want to store Binary files in STlink-V3 Or any other model , to flash the target on the field without host PC / Cube Programmer.I came to know , this device model has Bianary / hex file drag and drop feater , would it helpful in my scenario ?If not , Suggets any other option. 

Hello,Has anyone seen ACTCLF permanently stuck at 0 on STM32N6 despite a confirmed HS clock at the input?I have had issues with this for some time and need a little help. Pehraps the following questions could be enligtning.Are there SNPS D-PHY initialization or calibration steps for the clock lane beyond what HAL_DCMIPP_CSI_SetConfig performs? Clock-lane equivalents of the 0xe2–0xe4 DDL registers? Can ST confirm the CSI kernel clock (IC18) is the D-PHY cfg_clk, and its required range? The CCFR encoding caps at ~33 MHz and the DK example uses 20 MHz, but we couldn't find this constraint stated in RM0486. Is PTSR being permanently 0 expected on this silicon? Is there any way to verify test-interface writes landed? What exactly are the conditions for ACTCLF to assert? Does the RX require observing a complete LP-11 to LP-01 to LP-00 entry sequence after PEN, and is there a known failure mode if the LP levels at the pad are degraded (e.g., loaded by an external common-mode filter) while HS

Hello, We’re trying to program a STM32WBA23KE controller using SPI. We use the same function for STM32WB10 over SPI and it works.We’ve connected the SPI bootloader pins PA0/PA5/PB8/PB9 according to AN2606, where it mentions these are the pins used for QFN32 packages.We’ve also replaced an older part with an old date code to date code 620 because of the bootloader issue mentioned in the errata (should have been fixed since date code 614).We also have the PH3-BOOT0 pin connected and the NRESET. Still, we can’t get the bootloader to respond to the SPI sync command. What are we missing?

I create one project for STM32F401 DMA-TIM4_PWM, so far first DMA work, but it didn’t go to handle routing.After debug with Copilot help, find after DMA finish(set DMA_S0CR bit 0 to 1), the ISPR0 bit 11 set to 1, (it related with DMA1-s0.) but code didn’t jump to the vector in 0x6C (DMA1-so interrupt handle).If add one line force ISR0 bit 11 to 1, (NVIC->ISPR[0] = (1 << 11);),  IABR0 bit 11 set to 1. jump to handle routing.Why manual set work, use DMA_S0CR bit 0 to 1 doesn’t work (it same set  ISR0 bit 11 to 1 as manual.)?

Hello,I designed a custom 4-layer PCB using STM32WB55CGU6. After assembly, ST-LINK cannot detect the MCU.ST-LINK connection:- SWDIO connected to MCU SWDIO pin- SWCLK connected to MCU SWCLK pin- GND connected- Target VCC connected- ST-LINK reports target voltage around 3.25 V- Error message:  "Unable to get core ID"  "No STM32 target found"Main symptoms:1. The board has 3.25 V on the 3V3 rail.2. ST-LINK cannot connect to the MCU.3. PA10 is configured as GPIO output high to drive LED1, but PA10 voltage is only about 2.18 V.   - R8 MCU side: 2.18 V   - R8 LED side: 2.15 V4. The same firmware works on another known-good board.5. I replaced the STM32WB55CGU6 with a known-good chip, but the issue remains.   The removed chip still works on another board, so the MCU itself does not seem damaged.6. Current consumption comparison:   - Known-good board: about 23 mA   - Problem board: about 9.2 mA   - Known-good board while holding RESET: about 12 mA   - Problem board while holding RESET: about 3

i am using stm32h753zi and stmcubeide is 1.10.1 .the eth dx and rx is 30000000 and 30000200 and heap is 30044000 and rcc- bypass and used tim6  .i did it like the examples and i got no out and finally got a working code from claude, but it works only untill the power line is connected after i remove and reconnect it stopped working or works for one ping and stops .i thought may be it was beacause i used ramd2 and used ramd1 it also stops working when this stops.someone pls help me fix this i am willing to start from scratch lwip i used static ip address and pc is in same subnet/* USER CODE BEGIN Header *//** ****************************************************************************** * @file : main.c * @brief : Main program body ****************************************************************************** * @attention * * Copyright (c) 2026 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICEN

 Hi , Subject: i need to reduce the log write time what to do I have an STM32H503 logging ~20 bytes per line (HH:MM:SS , X.X) to a 24Cxx EEPROM over I2C @ 400 kHz, with FAT12 + USB MSC.Blocking time = the main loop stalls ~100–200 ms on each append while EEPROM writes finish.Each line only adds ~20 B of text, but my FAT code does full 512 B sector read-modify-write on the data sector, again on the root directory (file size), plus metadata read/write.That’s ~1 KB+ programmed per line (many 64 B page programs), so EEPROM ACK/program time dominates — not the 20 B payload or I2C speed alone.Basic issue: small appends through sector-based FAT on page EEPROM → huge writes per line.I’m thinking: defer root/meta to session end (back button), RAM cache, write only dirty 64 B pages.Is that the right fix? Can others get ~20–50 ms/line on 24Cxx without dropping FAT?

 As per my custom board pins(I am using single QUADSPI STR) I have selected and i tried to flash via Cube-Programmer CLIVEONE - MT25QL512_STM32H7XX-PB2-PB10-PF8-PF9-PF7-PF6.stldrhttps://github.com/cturvey/stm32extldr/blob/main/h7_mt25ql512a/CLIVEONE-MT25QL512_STM32H7XX-PB2-PB10-PF8-PF9-PF7-PF6.stldrISSUE : flash protection enabled https://github.com/cturvey/stm32extldr/tree/main/h7_mt25ql512aISSUE: I have tried with this external loader but i am not able to erase memory ​

When I compile my code, I get strange errors that make no sense.#define ADC_BUFFER 1000 gives error "expected declaration specifiers or '...' before numeric constant"even though the line above it #define ADC_HIGH_THRESHOLD 3500 doesn't generate an error.HAL_TIM_Base_Start(&htim3); and HAL_ADC_Start_DMA(&hadc1, (uint32_t*)adc_buffer, ADC_BUFFER); both generate "Syntax error".The TIM and ADC Start errors expanded error message is:  error: expected declaration specifiers or '...' before '&' token /* USER CODE END Header *//* Includes ------------------------------------------------------------------*/#include "main.h"/* Private includes ----------------------------------------------------------*//* USER CODE BEGIN Includes */#include <stdlib.h>#include <stdio.h>#include <stdbool.h>#include <stdint.h>#include <inttypes.h>#include "globals.h"/* USER CODE END Includes *//* Private typedef -----------------------------------------------------------*//