STM32 MCUs

hi We are using the STM32F103CBT6 as the ST-Link controller in our new gateway board.In the first version of the board, the ST-Link did not work as expected. We have made some changes, and this is the second version of the board.Could you please review the ST-Link schematic section and let us know if there are any issues or recommended changes? Your feedback would be very helpful in ensuring that the ST-Link works correctly in this version.Thank you in advance for your support.

Hi,I am configuring the STM32L412KB to operate as an SPI1 slave in 3-wire (1-line / half-duplex) mode.I have configured the following pins:PA4 → SPI1_NSS PA5 → SPI1_SCK PA6 → SPI1_MISO / SDIOWith this configuration, the SPI communication works correctly.However, in a previous support case with ST, I was advised to use PA7 as the SDIO pin. The information I received was:“On SPI1, the single data line in 1-LINE (half-duplex) mode is the MOSI pin = PA7.”According to the STM32L412KB datasheet, PA7 is indeed the SPI1_MOSI alternate-function pin, while PA6 is SPI1_MISO.However, when I configure PA7 as the SDIO line, the communication does not work. It works correctly only when I use PA6 as the SDIO line.Could someone clarify this behavior?In particular, I would like to understand whether, in SPI1 slave + 1-line (half-duplex) mode, the bidirectional data line is actually expected to be connected to PA7 (MOSI), or whether PA6 (MISO) can/should be used in slave mode.If there are any specific SP

From the documentation it sounds like the STM32WB vectors to the reset hander when it exits STANDBY and lower power modes, correct? 

Good afternoon,We are working with STM32H7A3 boards and are currently migrating our build and flashing toolchain from STM32CubeIDE 1.9.0 to 2.2.0. During the migration we ran into a flash programming failure that we have traced to the device description, and we would like your confirmation before we adopt a workaround.WHAT WE OBSERVEProgramming at 0x08100000 is rejected with "Operation exceeds memory limits" under 2.2.0. The same operation succeeded under 1.9.0.Investigating this led to two findings on Device ID 0x480:STM32_Prog_DB_0x480.xml declares the Bank 2 base address for the 1 MB configuration as 0x08080000, which contradicts RM0455 Rev 13, Table 15, and consequently excludes the documented Bank 2 base at 0x08100000 from the valid range; Writes to 0x08080000 are accepted and verify successfully on our samples, despite Table 15 listing that range as not mapped.FINDING 1 - DEVICE DESCRIPTION FILEThe file defines two configurations for Device ID 0x480, corresponding to the 2 MB and

Hi,I’m trying to configure Cube MX to drive this display - https://www.dxqdisplay.com/product/1-75-inch-466466-round-amoled-display-oncell-touch-qspi-interface-700-nits-31-pins-co5300-driver-ic-for-smart-watch/, from an STM32U5G9VJT6Q.Are there any examples for DSI displays on the STM32U5xx series MCUs that can be referenced as a good starting point? 

Hi everyone,I'm currently working on a project using an STM32H533RET6, and I am running a bit short on available pins. I am considering reconfiguring PA13 (SWDIO) and PA14 (SWCLK) to use them as standard general-purpose I/Os for my application.My main concern is about the flashing process. If I reconfigure these pins as regular GPIOs in my firmware, the SWD interface will be disabled as soon as the code starts executing.My questions are: Is it generally possible to use PA13 and PA14 as regular GPIOs and still be able to flash new firmware onto the MCU? If yes, what is the best practice to avoid permanently locking myself out? Do I strictly need to connect the hardware NRST pin to my programmer (ST-LINK) and use "Connect under reset"? Are there any software tricks (like adding a delay before GPIO initialization) that you would recommend? Obviously, I know that live debugging won't be possible once the pins are remapped, but I just need to make sure I can still update the flash relia

Hello,As indicate in the title I am trying to supply the MCU STM32L053R8 at 1.8V on the devkit NUCLEO-L053R8.To do it I opened Jumper JP6, which purposes is to monitor current, and I deliver 1.8V on the VDD signal.But the MCU is not working when I do that, my power supply is able to show me consumption and it stays to 0. I need to level up at minimum 2.8V to see some current consumption.Is there anything in particular  I need to disconnect to be able to power it at 1.8V ? I’ve tried to open SB21 to disconnect the Green Led connected to the MCU but it did not change anything. Also, I’ve try every power range and using MSI RC as SYSCLK.Please found attached my firmware which is, basicaly, only a while(1). Best RegardsThibaud

I am struggling to get TouchGFX running on my custom board. The processor is the STM32H7A3RGT and I am driving a 320 pixel x 960 pixel LCD display. I have allocated a frame buffer in internal RAM and have LTDC producing PCLK, DE, VSYNC and HSYNC. I have configured my firmware using CubeMX to use FreeRTOS. I added a call to MX_TouchGFX_Process in my default task but it gets stuck on an assert. Specifically here:Call StackThe reason it gets stuck is because pxQueue->ixItemSize is not zero !ASSERT in xQueueSemaphoreTakeWhat am I missing ?Andy

My MCU is H7R7, the image type in touchgfx designer only have RGB565 and ARGB8888, no L8 type.Framework features can not be changed.What is wrong with that?

Hello,I followed your reference and completed all the steps you mentioned before the screenshots. How to display an image stored in external flash on the STM32H7S78-DK using the LTDC controller  However, I have two issues:Could you please provide a clear, high-resolution screenshot of Tools → Memory Management? The previous screenshot was not clear enough for me to read the settings. I am unable to flash the Appli project onto my STM32H7S78-DK.   This is what I did:Initially, I cleaned both the Boot and Appli projects. I built only the Boot project and flashed it onto the STM32H7S78-DK successfully. Then, I built the Appli project. When I try to flash the Appli project, I am unable to flash it onto the board. Could you please explain step by step how I should flash both the Boot and Appli projects on the STM32H7S78-DK?Could you please provide a clear, high-resolution screenshot of Tools → Memory Management?

I am attempting to use the Nucleo-H723ZG with Ethernet and LWIP but without FreeRTOS.I am currently using STM32CubeMX 6.18.0 and STM32CubeIDE 2.2.0.I have spent weeks attempting to get this working following the various youtube videos and topics on here.I am currently attempting a simple UDP message that can be viewed on wireshark along the lines o “H723ZG with an incrementing counter”. I am unable to get any ARP or UDP currently.Any help is greatly appreciated - thanks.

MCU: STM32H753VIT6CPU clock: 480 MHzOS: FreeRTOSQuestion:In idle (no application workload, just FreeRTOS idle), the MCU package temperature is about 53°C.I measured this with a thermal camera.Is this temperature range expected/normal for STM32H753 at 480 MHz in idle?Or should I expect a significantly lower temperature?Additional notes:- No heavy application tasks running (idle-dominant)- Measurement method: thermal camera (not estimated)Any reference values or known typical idle temperatures for H753 at 480 MHz would be appreciated.Thanks.

I’m exploring ways to use an STM32 microcontroller for a smart home lighting project. The goal is to control multiple lights while monitoring switches and sensors, with reliable communication between the controller and other devices.I’m considering using STM32CubeIDE for development and would appreciate advice on choosing the right STM32 series, GPIO configuration, communication protocol, and a good starting architecture for this type of project.What STM32 development approach would you recommend for a beginner working on a smart home automation project?

I’m trying to migrate a project from the P NUCLEOWB55 MB1355 board to the P NUCLEOWB55 MB-1293 USB dongle.I retargeted the board in MX & check the pinouts etc, all fine. Opened up the project in CubeIDE & built the project.I then switched the board to BOOT0=0 (SW2) & plug it in & open CubePrgFirst issue, its really hit & miss if Prg detects the board. Most often I get Port: No DFU detected but then sometimes I actually get Port: Port 1 and the board can be connected to. It really appears to be pot luck if Prg decides it can connect.If I do manage to get it to connect, I update the FUS & stack, press the Start Stack button as outlined in a previous question, and continue to upload my *.elf file.Second issue, I get nothing from the BLE, no advertising at all. This project works fine on the MB-1355 board by the way.

 You can currently set tick rate using setVsyncInterval().I want to be able to get the tickrate using getVsyncInterval(). This would make timing things in the gui easier (blinking cursor, animation speed, boot logo, etc.). I made a topic about this earlier, but it got closed. 

I am using TIM1 CH1 in PWM mode with the TIM1 repetition counter (RCR) to generate a finite number of STEP pulses for a stepper motor. The desired step frequency is calculated from the motor speed, and ARR/CCR1 are configured accordingly. RCR is set to steps - 1 so that the PWM should generate the requested number of periods and then stop.I am using HAL_TIM_PWM_Start() and the TIM1 update interrupt to detect when the required number of pulses has completed. The update callback is working correctly and HAL_TIM_PeriodElapsedCallback() is being called at the expected completion point.However, TIM1 CH1 is not generating the PWM pulse train correctly, or in some cases no PWM is visible at all on the output pin. I have tried configuring PSC, ARR, CCR1, RCR and the update event/flags before starting PWM, but I am still unable to get the finite number of PWM pulses reliably.I have attached my motor_driver.c file for reference. Could you please review the implementation and let me know if I am

at stm32wl33 datasheet there is RX sensitivity topic but i think wrong– RX sensitivity @ 1% BER:◦ -132 dBm @300 bit/s 433 MHz OOK◦ -128 dBm @300 bit/s 868 MHz 2(G)FSK◦ -112 dBm @38.4 bit/s 868 MHz 2(G)FSKit should be kbit/s .  

I am designing a custom board using the STM32WL55 in UFBGA73, operating at 433 MHz, and I am currently facing higher-than-expected TX current consumption together with lower RF output power.I would like to know whether ST can provide load-pull data, optimum complex load impedance, or PA matching information at 433 MHz, particularly for approximately 0 dBm and +14 dBm TX power.I have compared my custom board against an STM32WL Nucleo board using the same firmware and RF settings.My measurements so far are:Nucleo board TX current: approximately 65.8 mACustom board TX current: approximately 72 mADifference: approximately 6–7 mA higher on my custom boardConducted RF power measurement on my custom board indicates approximately 10 dB lower output power than expectedMy next step is to measure the impedance presented to the PA at the beginning of the RF matching network and determine whether the PA is seeing the correct load at 433 MHz.Ideally, I would like to compare my measured impedance wit

Hi,We’ve been trying to implement secure-boot on our STM32H573-based device and the new code boots fine when the product state is OPEN. From what I understood, the PROVISIONING state does not boot the user code, and we thus need to put the device in iRoT-Provisioned to see if our boot chain works as expected.More info about our setup: Part: STM32H573AIIxQ DBGMCU_IDCODE (0x44024000): 0x10076484 Boot: STiRoT (BOOT_UBE=0xC3), TZEN=0xB4 Layout: secure app at 0x0C000400 (24 KB), non-secure app at 0x08006400 Software: STM32CubeMX-generated project, STM32Cube H5 HAL Debug: ST-LINK + OpenOCD, debug authentication (certificate chain), session reports Secure stateBack to the topic, I can see that te PKA register interface is fully alive, but the PKA compute engine never starts once thedevice is in iRoT-Provisioned product state. HAL_PKA_Init() spins in PKA_WaitOnFlagUntilTimeout() waiting for PKA_SR.INITOK, times out after 5 s, and the application lands in Error_Handler().The exact same binary a

Hello ST Community,We are optimizing background listener stability and remote webhook payload handling when integrating embedded telemetry data into enterprise management pipelines.Technical Setup: Our integration architecture at Frontline Sales Consultancy (flsc.co.uk) triggers automated B2B notifications and REST API syncs over HTTPS (TLS 1.3). The Issue We're Facing: Under heavy concurrent load spikes, background POST webhook listener sockets occasionally report HTTP 504 gateway timeout responses before acknowledging payload completion. Direct REST API requests to the same remote host resolve normally under 150ms thresholds. Are there recommended TCP keep-alive settings or queue worker retries to prevent connection drops during high-volume sensor/telemetry data syncs? Any advice on managing asynchronous background worker threads would be appreciated!Thanks!

Heyho,is there an overview when the cycle counter (DWT->CYCCNT) keeps running in which sleep modes?Or can anybody tell me?This info is spread over all kinds of documentation, and AI doesn’t give me a clear answer.Thanks!

Hi there, I am trying to to set up IEEE 1588 PTP time synchronisation with the Netx Duo IP-Stack. I want to port the STM32N6 example (https://github.com/STMicroelectronics/STM32CubeN6/tree/main/Projects/NUCLEO-N657X0-Q/Applications/NetXDuo/Nx_PTP_Client) to my STM32H563 / Nucleo-H563ZI.To my understanding, the H5 Series support PTP and should be able to run the example. The programm runs and prints out the MAC-clock, but the time does not increment and stays always on the same value of 0 seconds and 0 nanoseconds.I also tried to examine the PPS Signal on PG8 with an oscilloscope but as there is no running MAC clock, I get no PPS Signal.To fix this issue I tried different clock increments, thread-priorities. My guess is that the PTP clock in the MAC and the PPS output have to be activated seperately, but I wonder how? Thanks

The reason why TIM14->CCR1 = 50 and TIM9->CCR2 = 49 coexist1. Background and Configuration· Chip: STM32F407ZGTx· Connection: TIM14_CH1 (PF9) outputs PWM, connected via jumper to TIM9_CH1 (PE5) for input captureTIM14 (PWM output) configuration:· Clock 50 MHz, prescaler 4999, counting frequency 10 kHz· Up-counting mode, ARR = 199, CCR1 = 50· PWM Mode 1, active highTIM9 (input capture) configuration:· Clock 50 MHz, prescaler 4999, counting frequency 10 kHz· Slave mode: Reset mode, trigger source TI1FP1 (rising edge)· CH1: rising edge direct capture (CCR1)· CH2: falling edge indirect capture (CCR2)2. Observed PhenomenonIn the capture interrupt, the following registers are read:```cuint16_t IC1_Width = __HAL_TIM_GET_COMPARE(&htim9, TIM_CHANNEL_1); // TIM9->CCR1uint16_t IC2_Pulse = __HAL_TIM_GET_COMPARE(&htim9, TIM_CHANNEL_2); // TIM9->CCR2uint16_t CCR       = __HAL_TIM_GET_COMPARE(&htim14, TIM_CHANNEL_1); // TIM14->CCR1```LCD display results:Register Value Meaning

Hello everyone,I am currently evaluating the STM32H563 (using the NUCLEO-H563ZI board) with an application that sends a continuous UDP packet stream via 100 Mbps Ethernet.I've noticed that right after startup (or after flashing the board), the MAC drops a number of packets. Upon closer analysis, the MAC's TX buffer fills up completely, causing all subsequent packets to be dropped. After about 1 second, the MAC seems to stabilize, adjusts to the continuous packet flow, and begins sending all packets without loss.My questions: Why does this behavior occur? My suspicion is that the MAC might be operating in a low-power or standby mode initially, and takes a moment to ramp up to a continuous flow. Is this assumption correct? Is there a way to configure the MAC so that it operates at full speed right from initialization? Thank you for your insights!Best regards,Engineer 0815

Hi, I’m having trouble getting valid ciphertext and tag from the AES peripheral in AES GCM mode using the HAL. I know that some HALs for other chips have resolved the tag mismatch issue (e.g., STM32H7xx - AES GCM Invalid Tag Generation after Decryption). It appears that issue was resolved by accounting for the data swapping when zero padding a final block inferior to 128 bits. I applied a version of the fix to my code (based on both reference manuals the interface to the AES is nearly identical) but I’m still having tag issues. I noticed that before and after this fix zero padded words were being written to the AES input register last. Figure 73 on p369 in the RM0511 Reference Manual seems to imply that zero padded words should be written BEFORE the valid words of the block. Am I misinterpreting the figure?Tag and padding aside, I’m not even able to produce valid ciphertext compared to another implementation of AES GCM (python cryptography library). I use the same 128-bit key, the same