STM32N6 Nucleo XIP clock frequency problem.

[GoranDragovic]

Hello everyone,

I’m using Nucleo STM32N6 for a project of mine, and I used template XIP to begin with.
In template XIP, clock frequency of the XSPI2 is set to 50Mhz without any prescalers, and VDDIO3 is set to 1 (1.8V). That setup works fine for XIP up to 85Mhz clock frequency, but above that at BOOT (00) it fails as soon as it tries to jump to a application. 
I haven’t been able to resolve this problem. Is it setup, or something with EXT_MEM middleware?

In MX25 datasheet it can be seen that frequency heavily depends on dummy cycles, and 86Mhz corresponds to 8 dummy cycles, but on 200Mhz it requires 20. In EXT_MEM setup there is a 8D8D8D case where i go into during setup and it sets object to 20 dummy cycles, but I’m not sure is it successful in actually forcing that setup. 

Any help would be welcome.

 

[KDJEM.1]

Hello ​@GoranDragovic ;

 

Could you please check if HSLV_VDDIO3 is set to 1.

Please look at this article How to program the OTP fuse bits in the STM32N6 | Community to know how to check HSLV_VDDIO3 value.

 

Than k you.

Kaouthar

 

[GoranDragovic]

Yes, it is set. 

I have two STM32N6 Nucleo boards, on one I set HSLV_VDDIO3 to 1, and on second I set both HSLV_VDDIO2 to 1 also, and they both experience similar problems.

Picture of OTP124 for the board I’m currently using. 

 

[KDJEM.1]

Hello ​@GoranDragovic ;

 

You can check the number of dummy cycles in XSPI_TCR register CCYC[4:0] bits.

Are you able to run these examples STM32CubeN6/Projects/NUCLEO-N657X0-Q/Examples/XSPI?

 

Thank you.

Kaouthar

[GoranDragovic]

Okay, first of all, thank you for your engagement.

I ran XSPI_NOR_MemoryMapped_DTR example, and it is blinking GREEN, but weird part is CLK 200Mhz but Dummy Cycles set to 6, while the MX25 chip datasheet clearly says it should be 20. Also this RUNS code from RAM, it doesn’t to XIP as my code does. 

After that I ran my code that uses EXT_MEM, and with 80Mhz, it sets Dummy cycles to 20 in FSBL, after jump to APPLI, it sets dummy cycles to 10.

Later I set it to 200Mhz, and Dummy are still at 20 but, it fails to jump from FSBL to APPLI.

So I think it’s probably something with XIP handoff.

[KDJEM.1]

Hello ​@GoranDragovic;

 

For XSPI_NOR_MemoryMapped_DTR example, the XSPI  clock is 100MHz not 200MHz.

The Clock Prescaler = 1 → The prescaler is used to divide the source clock of the XSPI peripheral (f_) to obtain a frequency compatible with the external flash.

The formula is: f_CLK = f_Kernel/Prescaler+1

Where: 

• f_CLK = frequency applied to the memory on the XSPI lines
• f_ Kernel= clock frequency provided to the XSPI peripheral by the MCU

After that I ran my code that uses EXT_MEM, and with 80Mhz, it sets Dummy cycles to 20 in FSBL, after jump to APPLI, it sets dummy cycles to 10.

→ Could you please check the frequency and the dummy in XSPI registers and share values?

 

Thank you.

Kaouthar

[GoranDragovic]

Okay, I will give you snippets.

This is the FSBL part of the code: 

/* USER CODE BEGIN BSP */

/* -- Sample board code to send message over COM1 port ---- */

printf("Welcome to STM32 world !\n\rBoot project is running...\n\r");

/* -- Sample board code to switch on leds ---- */

BSP_LED_On(LED_BLUE);

BSP_LED_On(LED_RED);

BSP_LED_On(LED_GREEN);

CLK = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_XSPI2);

PRESCALER =

(XSPI2->DCR2 & XSPI_DCR2_PRESCALER_Msk)

>> XSPI_DCR2_PRESCALER_Pos;

printf("FSBL CLK: %lu \r\n", CLK);

printf("FSBL PRESCALER: %lu \r\n", PRESCALER);

printf("FSBL Dummy: %lu \r\n", XSPI2->TCR);

/* USER CODE END BSP */

/* Launch the application */

if (BOOT_OK != BOOT_Application())

{

Error_Handler();

}

/* Infinite loop */

/* USER CODE BEGIN WHILE */

while (1)

{

/* USER CODE END WHILE */

/* USER CODE BEGIN 3 */

}

/* USER CODE END 3 */

 

It’s similar with APPLI too and there is response in the picture attached at the bottom when CLK is 80 MHZ.

When I switch CLK to 200Mhz, it fails to jump to APPLI
 

[KDJEM.1]

Hello ​@GoranDragovic ,

 

I’m waiting for registers values.

Also could you please look at the errata sheet and try to disable the I/O compensation cell (EN = 0, CS = 1) on the relevant power domains (VDD, VDDIO2, VDDIO3, VDDIO4, and VDDIO5) and to use fixed compensation values for the RAPSRC[3:0] and RANSRC[3:0] bitfields. 

Thank you.

Kaouthar

[GoranDragovic]

Values are in the attachment from the answer above. This is the values that are displayed. 

CLK = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_XSPI2);

PRESCALER = (XSPI2->DCR2 & XSPI_DCR2_PRESCALER_Msk) >> XSPI_DCR2_PRESCALER_Pos;

printf("FSBL CLK: %lu \r\n", CLK);

printf("FSBL PRESCALER: %lu \r\n", PRESCALER);

printf("FSBL Dummy: %lu \r\n", XSPI2->TCR);

I will try that also, but I also started one more thread in hopes of getting more answers that can provide more information.