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Title: Hello,I am investigating BootROM behavior on an STM32N6570-DK.My expectation is based on the STM32N6 BootROM documentation and errata:- PG10 is used as BootFailedn in blocking failure conditions.<sup class="chatgpt-doc-sup"><span title="ES0620-STM32N6_Rev4.pdf, page 7" /></sup>- There is a known erratum: “PG10 (BootFailedn) signal not maintained at 1 during blocking failure”, with no workaround listed.<sup class="chatgpt-doc-sup"><span title="ES0620-STM32N6_Rev4.pdf, page 7" /></sup>Observed behavior on my board:- If the content of the OctaFlash is erased, I do not receive the expected serial BootFail-related output on PG10 / USART5_TX.- Measuring PG10 with an oscilloscope, I see a ~4.3 MHz square wave instead.- I observe the same square wave again after setting BOOT1=1 and BOOT0=0 and then resetting the board.Additional context:- I found guidance that Development Boot mode can be relevant for programming/erasing external flash on STM32N6570-D

Hi,I have custom PCB with STM32WB5MMG, which has STM32WB55VGY. I want to update FUS and software stuck and I would like to confirm which start address is the correct one. Should it be the one from the column STM32WB5xxG(1M) (as the chip is STM32WB5MMG) or the one from column STM32WB5xxY(640k) (as the MCU is STM32WB55VGY)?  

Hello everyone,I am trying to use TLS 1.3 with Mbed TLS on an STM32H573 through the Secure Manager’s Global PSA API.At the moment, I am seeing the following errors: psa_sign_hash() / psa_sign_message()→ PSA_ERROR_NOT_PERMITTEDpsa_generate_key() / psa_import_key()→ PSA_ERROR_GENERIC_ERRORThe persistent ECC keys are provisioned with the required signing permissions, and both the Secure Manager and the non-secure application start correctly.Some TLS 1.3 HKDF operations had to be implemented locally because the PSA Crypto API version in use is 1.0 and does not provide separate HKDF-Extract and HKDF-Expand algorithms.My questions are:Are persistent ECC keys supported with psa_sign_hash() through the Global PSA API? Does the Secure Manager support volatile keys with psa_generate_key() and psa_import_key()? Are additional permissions or a Secure Module required? Is there a support matrix or an official TLS 1.3 example for this setup? Does anyone have experience with Secure Manager and MbedTLS

Hi,We are currently using the STM32H563ZIT6 microcontroller in our project. We would like to obtain the FIT (Failure In Time) / reliability data for this device for our reliability and FMECA analysis.Please share the latest available reliability data or the relevant ST document/reference.Thank you for your support.Best regards,Geetha Thota.

Hello everyone.My fight with STM32H7R7 continues.I'm trying to get the simplest example of triggering the EXTI interrupt on an STM32H7R7I8T6. I've run this thousands of times on other H7 series MCUs and never had any problems. I have a button and an LED connected to the MCU as shown in the diagram.Pin PC11 configured as below:/*Configure GPIO pin : PC11 */GPIO_InitStruct.Pin = GPIO_PIN_11;GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;GPIO_InitStruct.Pull = GPIO_NOPULL;HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);/* EXTI interrupt init*/HAL_NVIC_SetPriority(EXTI11_IRQn, 0, 0);HAL_NVIC_EnableIRQ(EXTI11_IRQn); I added to the Callback code as always:/* USER CODE BEGIN 4 */void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin){    if(GPIO_Pin == GPIO_PIN_11)    {        HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_12);    }}/* USER CODE END 4 */ Optionally, I also added lines in the Callback itself:/* USER CODE BEGIN 4 */void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin){ if(GPIO_Pin == GPIO_PIN_11) { HAL_GPIO_Togg

I’m just starting a new project using the STM32H563. It has 16 channels of DMA, 8 in GPDMA1 and 8 in GPDMA2. I have at least 11 peripherals I’d like to use DMA for, UARTs, I2C and CAN. That means 22 channels of DMA if I want to use DMA for RX and TX. Does it make sense, or will it even work to use DMA for the RX side of a UART (for example) and IT for the TX side?My goal is to eliminate or at least minimize blocking in my program. I care more about DMA on the RX side since I often don’t know how many bytes will be in the message from the peripheral. I’ve used character match on the STM32H7A3 to deal with that in the past and the H563 is supposed to support character match also. TX is easier since I always know how many bytes I’m sending. I understand I’m still using CPU cycles to TX in IT mode but I don’t think that will cause any significant issues (I hope).

Dear ST Team,I have a STEVAL-ESC002V1 board and tried to generate the source code using MC Workbench, but I could not find the STEVAL-ESC002V1 board in the available options.I also checked the ST website and found firmware support for the IAR IDE:https://www.st.com/en/embedded-software/stsw-esc002v1.htmlHowever, I need support for STM32CubeIDE.Could you please confirm if STM32CubeIDE support is available for the STEVAL-ESC002V1 and guide me on how to generate or obtain the source code for this board?Thanks & Regards,Prashant Gautam

Hello everyone,I need to design a board featuring two STM32 microcontrollers that must operate in sync. To ensure clock synchronization, I plan to use a single external crystal.My proposed hardware approach is: Connect the standard external crystal (HSE) to MCU 1. Route the MCO (Microcontroller Clock Output) pin of MCU 1 to the OSC_IN pin of MCU 2. Configure MCU 2 to use HSE Bypass Mode, leaving its OSC_OUT pin floating. Place a series damping resistor on the trace between MCO and OSC_IN to prevent ringing. Could you please confirm if this topology is the correct and officially recommended approach for STM32 devices? Thanks in advance for your time and suggestions!

Hello everyone.I'm creating a TouchGFX project for a custom PCB with an STM32H7R7I8T6. After initial compilation issues, I unchecked the "Generate Under Root" option in the project manager and managed to compile the empty project and upload it to the MCU. Now I want to add a driver for the GT911 touch panel. I add one file, gt911.h, to the "Appli/Core/Inc" location, and it's visible, but the gt911.c file in the "Appli/Core/Src" location isn't visible to the project. This is my first time using this project organization and I can't figure it out.Please help.

Hello everyone,I'm trying to configure the SAI and GPDMA peripherals on an STM32 to acquire audio from an I2S microphone. My goal is to capture a 32-bit, 2-channel audio stream at a 16 kHz sample rate, with the STM32 acting as the clock master. I've followed the steps below, but I'm running into two main issues:While the HAL_SAI_RxCpltCallback and HAL_SAI_RxHalfCpltCallback functions are being called, the acquisition buffer remains unchanged (full of zeros).I'm seeing a 16 kHz signal on all three I2S lines (SCK, FS, and SD), which is incorrect. The clock (SCK) should be much higher.Here's a summary of the steps I've taken:PLL4 Configuration: I've configured PLL4 to generate a 1.024 MHz clock (16 kHz * 64 = 1.024 MHz). This clock feeds into the IC7 peripheral.GPDMA1 Configuration: I've enabled the clock and interrupts for GPDMA1 Channel 0 and added a linked-list initialization.SAI1 Block B1 Configuration: I've set up the SAI handle for I2S standard, 32-bit data, 16 kHz audio frequency,

From my understanding all STM32N6 chips need a external flash chip and there's a static stage 0 boot loader.  So if this is true is there any limitation's on the brands of flash or speed/address bit size limitations? With the previous stage 0 bootloader for a different non ST product had a lot of limitation on the flash that could be used.* 16 bit flash address only* Only support a few brands of flash chips.  

I am trying to generate an interrupt when the HSP finishes a processing list so that I don’t need to poll it. However, I can’t seem to figure out how to do this.There are some things in the STM32U3 reference manual that make me confused:In section 19.4.12 HSP interrupt controller (HITC), there are four interrupt lines:• An interrupt line handling errors (hsp_err_it)• An interrupt line handling various hardware events (hsp_evt_it)• An interrupt line handling events generated by the SPE processing (hsp_fwevt_it)• A global interrupt is asserted when one of the previous interrupts is asserted (hsp_it)However, in Section 19.3 HSP Implementation, Table 143 shows that neither hsp_err_it, hsp_evt_it, nor hsp_fwevt_it are implemented in the U3 series. If this is the case, does that mean that hsp_it is just never asserted? Is it possible to notify the application when a processing list has finished without polling for a flag?Section 5.13.5 of UM3360: HSP processing functions says that the SET_FL

Hello Team, I am using STM32N657X0H3Q, I am planning to integrate external RAM; however, the mentioned standard PSRAM, APS256XXN-OBR-BG, is not readily available on the market, so I chose to upgrade to DRAM, APS512XXN-OB9-BG. Is this upgrade safe? Also, are there any alternatives to MX66UW1G45GXDI00 that can serve as a good NOR flash? Regarding the USB-C connection, I am using a much simpler structure here, where I have left the VBUS Floating(I do not intend to use this USB to drive anything or for power delivery, just using it to communicate with pc and STM32CubeIDE) as shown in the picture below. Can you please let me know if this is a viable USB connection and if it's good enough for communication with STM32CUBEIDE ? Thanking You

OK, thank you it is so easy to omit.Could you please help me with another issue on usbx: Default value for “CoreStack Device/Host” is “enable” but there is warning in red: The component “USBX/CoreSystem” must be selected alongside either “USBX/UX Host CoreStack” or “USBX/UX Device CoreStack”  Core Sytem is selected as you can see. Or is it referencing to some other component?  

I'm using a Macbook Air M5. I downloaded the STM32CubeIDE 2.2.0 macOS (Apple Native) version to my computer. After importing my projects, I tried to debug. It connects to the ST-Link and performs the necessary operations. Then, when debugging is ready, I start the debug and get this error: GdbSession, Lost target connection, Exiting... GdbSession, Lost target connection, Exiting... I checked the permissions on my Mac and updated the STM Link version. Also, when I install the Mac (Apple Native) version of STM32CubeProgrammer, I can program the same board using the ST-Link. The port is visible. And interestingly, when I open the same project on my Windows computer, I can debug it without any problems using the same ST-Link.Any advice on how to resolve this issue so I can debug directly from STM32CubeIDE would be greatly appreciated!Thanks in advance for your help.Best regards,

Hi,I'm bringing up a USB MSC device on an STM32U385CGT6 with the USBX middleware in standalone mode. Everything comes from CubeMX 6.18.0 with STM32Cube FW_U3 V1.4.0 (USBX 6.4.0): USB_DRD_FS in device mode, USBX Core System + UX Device CoreStack + UX Device Controller + UX Device MSC.While comparing the generated code and some example applications (NUCLEO-U385RG-Q Ux_Device_HID_Standalone) it looks there is a regression in the generated HAL_PCD_MspInit. While the version from the example application enables Vdd USB, this is missing from the currently generated version of HAL_PCD_MspInit causing the peripheral to remain powered down. As a fix HAL_PWREx_EnableVddUSB(); can be called in the user code section at the bottom of HAL_PCD_MspInit. Best Regards, Cecil

I am following these steps :- Create STM32 ProjectFile → New → STM32 ProjectSelect STM32L476RGTx (LQFP64) MCU/board → Next → FinishOpen the .ioc fileConfigure LED1In Pinout & Configuration, Set PA2 to GPIO_Output, then click on project → generate code ( The ‘main.c’ file is not generate for given MCU and also for other MCU for similar steps code is not generating).  

I have the X-NUCLEO-53L9A1 board and NUCLEO.H563ZI. I load the binary provided by ST (53L9A1_PostprocessSingle.bin) and I attach what I get in the serial terminal. I was expecting different data, like a distance value array that I could draw as bitmaps. How is this supposed to work? 

Hi, I got a black pill. It says everywhere that to enter DFU mode, you have to keep pressing BOOT0, then press and release RST, then release BOOT0. But every time I do this, Cube IDE says ST-Link is not in the DFU mode, please restart it.

During the SMT process, air may get blown into the pressure port from the pick-and-place nozzle, will the sensor inside be damaged? 

Dear STM32 Advisor,   I'll design a system based on Nucleo 64 H533RE. The system will act as USB CDC and USB HID Keyboard at the same time. The idea is when the CDC receive a character, here for example "F" then the Nucleo H533RE will output a high going pulse. And, if the Nucleo H533RE receive falling pulse external interrupt, the the Nucleo H533RE will press the F8 key. As a beginner on STM32, is it possible?   Thanks and regards,   Fuad Purnomo.

I have a question regarding your company’s NUCLEO-H753ZI model.I evaluated two boards of this model (let’s call them a and b), and observed the following phenomenon exclusively on ADC channel 2 of board a. [Phenomenon]When we applied various input voltages and measured the output, we found that the output dropped by approximately 800 LSB (equivalent to about 0.04 V) within the input voltage ranges of 0.825–1.65 V and 2.475–3.3 V (1/4–2/4 and 3/4–4/4 of full scale).*The input voltage conditions (accuracy, ripple) were identical across all boards and channels. [Board Information]ADC Channel 2 Assignment: PA3Resolution: 16-bit modeSampling Time: 16.5 cyclesSampling Frequency: 250 kHz (timer-triggered) Since this phenomenon is not observed on other boards or channels, we suspect that some kind of malfunction is occurring. Based on the symptoms, we also suspect a failure within the successive approximation ADC. If you know the cause of this phenomenon, please let us know.Also, if there are

HiI recently received a NUCLEO-WB55RG (the big board, not the USB dongle) and tried installing the demo from the STM32CubeWB repository.I saw that I need to flash the FUS + Stack first which I did. STM32CubeProg reports FUS State: FUS_IDLEFUS Status: FUS_NO_ERRORFUS Version: V2.2.0.0STACK Version: V1.24.0.3STACK Address: 0x80D0000FUS Operator: v3.1.0The files I flashed were:STM32CubeWB-master\Projects\STM32WB_Copro_Wireless_Binaries\STM32WB5x\stm32wb5x_BLE_Stack_full_fw.binSTM32CubeWB-master\Projects\STM32WB_Copro_Wireless_Binaries\STM32WB5x\stm32wb5x_FUS_fw.binAs application I chose the p2pServer applicationSTM32CubeWB-master\Projects\P-NUCLEO-WB55.Nucleo\Applications\BLE\BLE_p2pServer\Binary\BLE_p2pServer_reference.hexWhen I disconnect the SWD Interface and press the reset button I get the following output (nothing else):Wireless Firmware version 1.24.0 Wireless Firmware build 3 FUS version 2.2.0 >>== SHCI_SUB_EVT_CODE_READY >>== SHCI_SUB_EVT_CODE_READY - FUS_FW

Currently we are developing an AI Industrial camera using STM32N6570, we are exploring the compatible SPI Flash for the implementation. Could you share your recomendation of 1Gb Octal SPI Flash.

Hello,I have encountered a critical issue regarding the USB OTG peripheral FIFO allocation during the static initialization phase (before calling HAL_PCD_Start() ).The Issue:If I resize the Rx/Tx FIFOs twice with the sequence of "Large Size first, then Small Size", the Endpoint 0 (EP0 IN) completely fails to transmit any data (it freezes/stalls) after the hardware starts.Scenario A (Works perfectly): Set Rx FIFO to 0x100 (Words) ➡️ Set Tx FIFO 0 to 0x16. (Single configuration works). Scenario B (Fails completely): First call: Set Rx FIFO to 0x100, Tx FIFO 0 to 0x16. Second call (immediately after): Set Rx FIFO to 0x25, Tx FIFO 0 to 0x16.Result: EP0 IN never transmits any packet afterward.My ultimate goal is to dynamically reconfigure and shrink the FIFO layout at runtime when receiving the SET_CONFIGURATION request from the host, allowing the device to adapt to different configurations