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Hi everyone,I am new to the MCSDK environment and currently working on a porting project from MCSDK 5.4.8 to 6.4.1. I have been stuck on this for weeks and I am honestly getting desperate as I cannot find a way forward.I need a functional routine to handle encoder alignment that is compatible with the 6.4.1 framework. The alignment must be performed solely upon user request, and it is critical that the motor does not start running after the alignment sequence. I am looking for a direct replacement for the legacy MCAlignEncoderMotor1() API.I have already attempted the implementation suggested in this thread: MCSDK 6.3 - Correct way to restart / retrigger encoder alignmentUnfortunately, this solution does not work for my setup. Could you please provide guidance on how to trigger this alignment in isolation within the 6.4.1 architecture?Best regards,bolla_bo

Hello,I am working on a design incorporating the STM32U3C5CIU6Q in SMPS mode. This package includes two VDD11 pins. I am having trouble interpreting the datasheet when it comes to the number of inductors I will need. This note under Figure 24 in the datasheet is clear that each pin will need a capacitor to VSSSMPS, but it seems like it could also imply that each VDD11 pin requires its own inductor between VLXSMPS.The power supply scheme (with SMPS) is also not clear to me: This section seems more like it is expecting a single inductor:Am I okay to use a single inductor between the VLXSMPS pin and VD11 node, with each VD11 pin having its own capacitors, or should I treat each VD11 as a separate loop with its own inductor as well?Thanks for any help!

NUCLEOWB55RG I set I2C3 in MX. I have 2 x temp sensors & 2 x accelerometers in the bus./* Snippets of code to show how I2C3 is set up & used */#include "main.h"#include "adt7410.h"#include "adxl345.h"I2C_HandleTypeDef hi2c3;ADT7410 temp_0;ADT7410 temp_1;ADXL345 acc_0;ADXL345 acc_1;static void MX_GPIO_Init(void);static void MX_I2C3_Init(void);int main(void){ HAL_Init(); MX_GPIO_Init(); MX_I2C3_Init(); /* ADT7410 set up */ /* temp_0 at 0x48 * temp_1 at 0x49 */ temp_0.adti2c = &hi2c3; // I2C Handler ADT7410_Init(&temp_0, 0x48); // I2C address depends of A0 and A1 pins ADT7410_Reset(&temp_0); // Optional ADT7410_SetResolution(&temp_0, ADT7410_16BITS); // Put the device in 16 bits resolution temp_1.adti2c = &hi2c3; // I2C Handler ADT7410_Init(&temp_1, 0x49); // I2C address depends of A0 and A1 pins ADT7410_Reset(&temp_1); // Optional ADT7410_SetResolution(&temp_1, ADT7410_16BITS); // Put the

If I copy the MCU part number from the NUCLEO-C5A3ZG Product Page and paste into CubeMX2, it gets a trailing space - and says “No available options”: Removing that space does then give a list of 2 devices: It really should be able to cope with trimming whitespace from the input box!

Firmware Package: STM32Cube_FW_H5_V1.6.0 Product ProblemDA regression fails with timeout. I cannot recover the board. I was trying to run the STiROT Template example (STiROT_Appli) on the STM32H573I-DK board. 1. I ran a custom provisioning script (based on ob_flash_programming.sh + obkey_provisioning.sh)2. During image flashing step, I accidentally flashed an unsigned binary (appli.bin) instead of the signed image (appli_init_sign.hex)3. OBKey provisioning (DA_Config.obk, STiRoT_Config.obk, STiRoT_Data.obk) may have failed due to the MCU being in an unstable state4. I then set Product State to PROVISIONED (0x2E) Discovery output Discovery succeeds and shows- PSA lifecycle: ST_LIFECYCLE_IROT_PROVISIONED - ST provisioning integrity status: 0xf5f5f5f5 - ST HDPL1 status: 0x1 - Permission: Full Regression is listed as available Regression attempt Using default keys from the firmware package (not regenerated): - Key: DA/Keys/key_3_leaf.pem - Certificate: DA/Certifica

In RM0481 rev 4 April 2025 I find the following text:7.6.8 Write protectionA write-protected group of sectors cannot be erased nor programmed. As a result, a bankerase cannot be performed if one group of sectors is write-protected, unless a NVSTATEtransition to OPEN is triggered (erasing the whole user flash memory). It is not clear what NVSTATE is in this context. Is this a left-over from documentation of a different MCU? I don’t think it is PRODUCT_STATE. Because to my understanding you can have a PRODUCT_STATE > OPEN and not enable TrustZone and then write to FLASH_WRP1R_PRG to turn off write protection - you should be able to do a bank erase on bank 1. You can set initial values with an OB but I can’t see any documentation that this also makes changing FLASH_WRP1R_PRG illegal and the relevant OBs are not protected by PRODUCT_STATE the same way as e.g. SECWM and HDP.Same reasoning for flash bank 2.And if you enable TrustZone, it is stated that FLASH_WRP[1, 2]R_PRG is non-secure.

Hello ST Community,I am evaluating the security features of the STM32H733 (Cortex-M7) for a project that uses:A custom bootloader stored in internal flash The main application stored and executed from external QSPI/Octo-SPI flashI have the following questions regarding Secure Firmware Install (SFI):Is SFI for internal flash officially supported on the STM32H733? (I saw it was added in AN4992 Rev 8, but I would like official confirmation.) Is SFI for external flash (SFIx) supported on the STM32H733? Specifically, can the secure bootloader (RSS) decrypt and program the external application image securely during manufacturing, or is only the "host-side encryption + internal firmware configures OTFDEC" method available? If external SFIx is not supported, what is the recommended secure manufacturing flow for a design with main code in external flash?

Hi.I’m working on a custom board with a C551VET6 and trained on a NUCLEO_C562RE with ADC. I attempted the conversion in polling mode in several ways (mode=single + discountinuous=disabled  /  mode=continuous + discountinuous=3ranks) by varying the implementation of the FOR loop (including or excluding the calls to HAL_ADC_REG_StartConv and HAL_ADC_REG_PollForConv according to the selected mode); no matter what I did, as soon as I needed to convert 3 or more channels, only the first two showed distinct values, while all the other channels in the sequencer returned a value identical to that of the second channel.I found no example using more than 2 channels in a basic regular sequencer. Have you tried it at ST ?By the way, I’m working with a CTN temperature sensor and two HDC3120 giving both temperature and humidity, thus 5 channels in my case.Do I need to lower the resolution or something when the number of channel increases ?I’m not familiar with ST community mechanisms, shall I open a

Searching for “STM32C5A3ZG” (the part number stated on the NUCLEO-C5A3ZG Product Page), CubeMX v1.0.1 offers STM32C5A3ZGT6 and STM32C5A3ZGT7 The latest Datasheet (DS15137, Rev 2) does not list STM32C5A3ZGT7 as a valid ordering code, but it does have STM32C5A3ZGT3 - which is not in the CubeMX2 list:: 

Hi,I am trying to connect SDRAM AS4C16M16SB from Alliance Memmory to STM32N655X0 MCU, but i did not find any reccomended connection. I am “pinned” this memorry to MCU according STM32Cube MX software and MCU datasheet. But there is not much more information about “autoprecharge” function. Only in reference manual RM0486 is small note “The AutoPrecharge is not supported. However, FMC_A[10] must be connected to SDRAM A[0]”. But the memmory has dual function on the address 10 pin (address 10 + AP). Do you have some recommendation how this memmory connect to STM32N655X0 MCU, or is it suitable for this MCU?Below is my wiring diagram, in purple are FMC signals corresponding with pins on MCU. Is it right or am I must somehow reroute the address signal signal (A10)?Thanks a lot. R. 

Hi, Is there mistake between reference manual RM0486 and RM0090 in section SDRAM adress mapping?Where in RM0486 is: "When interfacing with a 16-bit memory, the FMC internally uses the ADDR[11:1] internal address lines to generate the external address. When interfacing with a 32-bit memory, the FMC internally usesADDR[12:2] lines to generate the external address. Whatever the memory width, FMC_A[0] has to beconnected to the SDRAM A[0].The AutoPrecharge is not supported. However, FMC_A[10] must be connected to SDRAM A[0]"In RM0090 is: "When interfacing with a 16-bit memory, the FMC internally uses the HADDR[11:1] internal AHB addresslines to generate the external address. When interfacing with a 32-bit memory, the FMC internally usesHADDR[12:2] lines to generate the external address. Whatever the memory width, FMC_A[0] has to beconnected to the external memory address A[0]. The AutoPrecharge is not supported. FMC_A[10] must be connected to the external memory address A[10] but it is alwa

This is a followup to the question: How to organize the folder structure in CubeMX-generated codeThere, the solution was by ​@Ghofrane GSOURI and the added comment by ​@Andrew Neil to keep your application code outside of CubeMX generated folders in structure like so:Project/├─ Core/ # CubeMX-owned│ ├─ Inc/│ └─ Src/├─ Drivers/ # ST/CMSIS├─ Middlewares/ # Optional (FreeRTOS, USB, etc.)├─ App/ # Your application logic│ ├─ Inc/│ └─ Src/└─ Framework/ # Your reusable firmware framework ├─ Inc/ └─ Src/Which make a ton of sense, but I am stuck at how to actually implement this in CMake. I let CubeMX generate a folder for CMake toolchain. That directory has these additional files/folder:Project/├── Application ## directories where my code would exist│   └── blinky│   └── blinky.c│   ├── blinky.h│   └── uart/│   └── ...├── cmake│   ├── gcc-arm-none-eabi.cmake│   ├── starm-clang.cmake│   └── stm32cubemx│   └── CMakeLists.txt├── CMakeLists.txt├── CMakePresets.json└── Core/...,

Previously I used Programmer v2.15 on H5 MCUs to zero (uncheck) nSWBOOT0. Probably due to Windows drivers updates, I could no longer connect.I updated to Programmer v2.23 and I can now connect, but I no longer see nSWBOOT0 anywhere. Where did it go?

Hi,I'm integrating an STSAFE-A110 with stsafe-a-openssl-engine V2.0.0 on a Linux/aarch64 host (Jetson AGX Orin, Ubuntu 22.04, OpenSSL 3.0.2), communicating over I2C. I've resolved a number of earlier issues (wrong I2C bus, OpenSSL 3.0 API migration, host key pairing) and now have Host Key programming, Local Envelope key generation, Product Data query, Life Cycle State query, and Command Authorization Configuration query all succeeding against the physical chip.Current issue: StSafeA_WrapLocalEnvelope and StSafeA_UnwrapLocalEnvelope behave asymmetrically.My chip's Command Authorization Configuration reports:Command 0x0E (Wrap Local Envelope): CommandAC = 0x03 (MAC), HostEncryptionFlags = 0x02 (command encryption) Command 0x0F (Unwrap Local Envelope): CommandAC = 0x03 (MAC), HostEncryptionFlags = 0x01 (response encryption)Calling Wrap with STSAFEA_MAC_HOST_CMAC, STSAFEA_ENCRYPTION_COMMAND succeeds and returns a plausible 488-byte wrapped envelope.Calling Unwrap on that same output with S

1. Is it possible to install two versions of STM32CubeIDE (e.g., 1.9.0 and 1.19.0 or 1.19.0 and 2.2.0) on one PC (Windows)?   If so, can I run both versions simultaneously?    If so, can I program two microcontrollers simultaneously with two programmers?2.Is it possible to install STM32CubeIDE and STM32CubeIDE for VS Code on one PC (Windows)?   If so, can I run both versions simultaneously?    If so, can I program two microcontrollers simultaneously with two programmers? 

Hello,is the breakdown voltage of a TVS (e.g. SMAJ5.0A) a guaranteed value?Background: I whish to protect a circuit from overvoltages on the 5V supply which can be normally range from 4.4V to 6V. AN316 would then suggest to use a  SMAJ6.0A or better 6.5A as it says, that the maximum operating voltage should be below the Vrm voltage.But if I read the datasheet right, the Vbr voltage states a minimum (tested?) voltage at which the reverse current reaches / exceeds 1mA.If I want to have the protection level as low as possible, I would prefer the SMAJ5, as it has a VBr of 6.4V. I know, if my supply goes up to 6V that I get a higher reverse current, which I can to tolerate. But I would expect, that this current is not higher than the test current of 1mA for the Vbr and therefore the dissipated power in the TVS should well below 10mW. Does an elevated voltage near to the breakdown voltage cause problems over time?

STM32CubeIDE v2.1.1 - ST-LINKV3 MINNIE latest version - FreeRTOS v10.3.1 - CMSIS-RTOS v2.1.3STM32G0B1METxWhen launching a debug session I get the following: “Target is not responding, retrying…”.If I remove any random part of my code, the issue goes away.I have been trying to adjust global heap/stack sizes, individual tasks stack sizes without success.Any insight would be appreciated.Thanks.

A customer asked for the process technology or process node in nano meters (nm) for the STM32F303CCT7 we use. I can not find any information on ST website. The “Sidekick” told me there is no information about. Can someone help me?

Hello,I am using the Nucleo STM32H533RE board for booting with the two stage boot path for which I am using the ST template code and referring the following   https://wiki.st.com/stm32mcu/wiki/Security:OEMiRoT_OEMuRoT_for_STM32H7S . I am able to run the provisioning script successfully but when I am connecting the serial terminal to verify the serial data sent out by the board, I am getting an error saying “[ERR] read:Wrong OBK HDPL2 cfg” as seen in below image:I tried with the following things:Regenerating the OEMuROT OBK files manually using stm32 trusted package creator Running the regression script to erase the flash and again running the provisioning script Verified if the key file names matches the script referencesCan someone help me with this issue.Let me know if any other details are required. Thanks,Amruta

Hello,I am working with an STM32N6570-DK board and facing an issue while setting up the SD card. I created a project using TouchGFX Designer, generated the code, and opened the .ioc file. In there, I enabled SDMMC2 with 4-bit Wide mode and enabled global interrupt:After checking the schematics, I noticed that the CK pin was incorrect, so I assigned the correct pin (PC2:(I made the following additional configurations:Changed all SDMMC2 pins to pull-up and set Max output speed to Very HighEnabled PWR_SD_EN (PQ7) as output level high with context FreeChanged clock from HCLK to IC4 (should not affect anything)Enabled SD_DETECT (PN12) to detect when the SD card is inserted or removedEnabled EXTI Line4 and EXTI Line12 for interruptsEnabled FileX with mostly default settings, except for increased memory and FX driver initialization:After this setup, I attempted to initialize the SD card with the following call:fx_media_open(&sdio_disk, "SDIO_DISK", fx_stm32_sd_driver, NULL, fx_sd_media_me

Hi,I am using LSM6DSV320X for my project. Initially to save power I have Low G accelerometer with 15Hz ODR and 16G with fifo enabled. Once an activity is detected i want to switch on High G as well with 4000 Hz (with High Accuracy mode) and use both high G and Low G accelerometer for data collection. Is this possible if I dont use FSM or ASC and will High Accuracy then work ?. or can this only be achieved with FSM ? I look forward to your reply.

Have any User Guide to setup matter in STM32WBA65RI? Matter 1.5.0 is supported in STM32WBA65RI?

I'm trying to configure and generate a project with STM32CubeMX for the STM32WBA5MMGHx BLE module.When enabling the STM32_WPAN middleware, the ADV_TRACE module gets automatically enabled under Utilities. This in turn requires to enable at least one UART/LPUART peripheral, otherwise type UART_HandleTypeDef is undefined and compiler throws and error:../../Core/Inc/app_conf.h:304:8: error: unknown type name 'UART_HandleTypeDef'; did you mean 'RTC_HandleTypeDef'? [build] 304 | extern UART_HandleTypeDef huart1; [build] | ^~~~~~~~~~~~~~~~~~ [build] | RTC_HandleTypeDefThe STM32_WPAN throws a warning about not configured/wrong Platform Settings.Is there any possibility to configure STM32_WPAN without ADV_TRACE enabled?Used STM32CubeMX version is 6.17.0 and WBA firmware v1.19.0 and cmake project is generated.

Board: STEVAL-MKI109D (STM32H563ZI) + STEVAL-MKI207V1 adapter (ISM330DHCX)Goal: Bare-metal custom firmware reading WHO_AM_I over SPI1Following up on my earlier thread about GPIO pin mapping [link to old thread] — pin mapping is now resolved (SPI1_NSS on PA15, confirmed via community input; PA4/PA5 are DAC1 Vdd_set/VddIO_set as discussed). Thanks for the help getting there.I'm now stuck on a different issue and would appreciate a sanity check. WHO_AM_I consistently reads 0xFF, but every layer I can verify from firmware/multimeter checks out correctly:CS on PA15 (GPIO output, confirmed via MODER/ODR register dump) SPI1 Mode 3 (CPOL=1, CPHA=1) — confirmed via CFG2 register decode SCK/MISO/MOSI on PB3/PB4/PB5, AF5 — confirmed via GPIOB MODER/AFRL dump VDD/VDDIO measured 3.3V at the DIL24 breakout header (J13/J14 area on JP1/JP2), in spec HAL_SPI_TransmitReceive returns HAL_OK, ErrorCode=0x0, every call — no timeout, no fault Tested at both SPI_BAUDRATEPRESCALER_32 and _256 (extremes) — ide

Hi,I am using the STM32N657-DK and running the NetX Duo WebServer example provided by STM32Cube. The application works correctly when the Ethernet link is negotiated at 100 Mbps and 1 Gbps. However, when the link speed is 10 Mbps, the web server is not reachable and communication fails.SetupBoard: STM32N657-DK Software: STM32CubeIDE / STM32Cube firmware NetX Duo WebServer example PHY: (RTL8211F-CG, if applicable) Interface: RGMIIObservations1 Gbps: Works correctly. 100 Mbps: Works correctly. 10 Mbps: Link appears to come up, but the web server cannot be accessed and network communication fails.QuestionsDoes the STM32N657-DK NetX Duo Ethernet driver fully support operation at 10 Mbps? Is there any additional MAC or PHY configuration required when the negotiated speed is 10 Mbps? Are there any known limitations or issues with the NetX Duo Ethernet driver or HAL Ethernet driver when operating at 10 Mbps? Has anyone successfully run the NetX Duo WebServer example at 10 Mbps on the STM32N65