Skip to main content
Visitor II
September 4, 2025
Question

STM32N6570-DK MIPI CSI-2 D-PHY Camera Issue

  • September 4, 2025
  • 2 replies
  • 491 views

Hello teams,

I tried to use STM32N6570-DK DCMIPP Pipe0 to read data from my camera that has own ISP. The camera output format is UYVY (YUV422 BPP16). The issue is that I can't get any data from DCMIPP and CSI-2 Host, I only received SOF and EOF events from CSI-2 Host. I've referred to other people's posts, but my issue still exists. Is my DCMIPP and CSI configuration wrong?

Additionally, I'm not sure if the CSI and DCMIPP clock is set correctly, I just follow the example. If my camera out is 640x480@60fps and format is UYVY, how should I configure this clock?

My settings are as follows.

static void MX_DCMIPP_Init(void)
{

	/* USER CODE BEGIN DCMIPP_Init 0 */

	/* USER CODE END DCMIPP_Init 0 */

	DCMIPP_CSI_PIPE_ConfTypeDef pCSI_PipeConfig = { 0 };
	DCMIPP_CSI_ConfTypeDef pCSI_Config = { 0 };
	DCMIPP_PipeConfTypeDef pPipeConfig = { 0 };

	/* USER CODE BEGIN DCMIPP_Init 1 */

	/* USER CODE END DCMIPP_Init 1 */
	hdcmipp.Instance = DCMIPP;
	if (HAL_DCMIPP_Init(&hdcmipp) != HAL_OK) {
		Error_Handler();
	}

	/** Pipe 0 Config
	 */
	pCSI_PipeConfig.DataTypeMode = DCMIPP_DTMODE_ALL;
	pCSI_PipeConfig.DataTypeIDA = DCMIPP_DT_YUV422_8;
	pCSI_PipeConfig.DataTypeIDB = DCMIPP_DT_YUV422_8;
	if (HAL_DCMIPP_CSI_PIPE_SetConfig(&hdcmipp, DCMIPP_PIPE0, &pCSI_PipeConfig)
	 != HAL_OK) {
		Error_Handler();
	}
	pCSI_Config.PHYBitrate = DCMIPP_CSI_PHY_BT_800;
	pCSI_Config.DataLaneMapping = DCMIPP_CSI_PHYSICAL_DATA_LANES;
	pCSI_Config.NumberOfLanes = DCMIPP_CSI_TWO_DATA_LANES;
	if (HAL_DCMIPP_CSI_SetConfig(&hdcmipp, &pCSI_Config) != HAL_OK) {
		Error_Handler();
	}
	pPipeConfig.FrameRate = DCMIPP_FRAME_RATE_ALL;
	pPipeConfig.PixelPipePitch = 10;
	pPipeConfig.PixelPackerFormat = DCMIPP_PIXEL_PACKER_FORMAT_YUV422_1;
	if (HAL_DCMIPP_PIPE_SetConfig(&hdcmipp, DCMIPP_PIPE0, &pPipeConfig)
	 != HAL_OK) {
		Error_Handler();
	}
	HAL_DCMIPP_CSI_SetVCConfig(&hdcmipp, 0U, DCMIPP_CSI_DT_BPP16);
	/* USER CODE BEGIN DCMIPP_Init 2 */

	/* USER CODE END DCMIPP_Init 2 */

}
void HAL_DCMIPP_MspInit(DCMIPP_HandleTypeDef *hdcmipp)
{
	RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
	if (hdcmipp->Instance == DCMIPP) {
		/* USER CODE BEGIN DCMIPP_MspInit 0 */
		RAMCFG_HandleTypeDef hramcfg = { 0 };
		RIMC_MasterConfig_t RIMC_master = { 0 };
		/* USER CODE END DCMIPP_MspInit 0 */

		/** Initializes the peripherals clock
		 */
		PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_DCMIPP
		 | RCC_PERIPHCLK_CSI;
		PeriphClkInitStruct.DcmippClockSelection = RCC_DCMIPPCLKSOURCE_IC17;
		PeriphClkInitStruct.ICSelection[RCC_IC17].ClockSelection =
		RCC_ICCLKSOURCE_PLL1;
		PeriphClkInitStruct.ICSelection[RCC_IC17].ClockDivider = 4;
		PeriphClkInitStruct.ICSelection[RCC_IC18].ClockSelection =
		RCC_ICCLKSOURCE_PLL1;
		PeriphClkInitStruct.ICSelection[RCC_IC18].ClockDivider = 60;
		if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
			Error_Handler();
		}

		/* Peripheral clock enable */
		__HAL_RCC_DCMIPP_CLK_ENABLE();
		__HAL_RCC_CSI_CLK_ENABLE();
		__HAL_RCC_CSI_FORCE_RESET();
		__HAL_RCC_CSI_RELEASE_RESET();
		/* DCMIPP interrupt Init */
		HAL_NVIC_SetPriority(DCMIPP_IRQn, 7, 0);
		HAL_NVIC_EnableIRQ(DCMIPP_IRQn);
		HAL_NVIC_SetPriority(CSI_IRQn, 7, 0);
		HAL_NVIC_EnableIRQ(CSI_IRQn);
		/* USER CODE BEGIN DCMIPP_MspInit 1 */
		GPIO_InitTypeDef GPIO_InitStruct = { 0 };
		__HAL_RCC_GPIOC_CLK_ENABLE();
		__HAL_RCC_GPIOD_CLK_ENABLE();
		/* CAM_NRST */
		GPIO_InitStruct.Pin = GPIO_PIN_8;
		GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
		GPIO_InitStruct.Pull = GPIO_NOPULL;
		GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
		HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);

		/* CAM_PWR_EN */
		GPIO_InitStruct.Pin = GPIO_PIN_2;
		GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
		GPIO_InitStruct.Pull = GPIO_NOPULL;
		GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
		HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);

		HAL_GPIO_WritePin(GPIOC, GPIO_PIN_8, GPIO_PIN_RESET); /* Off *//* PC8 CAM_NRST */
		HAL_GPIO_WritePin(GPIOD, GPIO_PIN_2, GPIO_PIN_SET); /* Off *//* PD8 CAM_PWR_EN */

		/* SRAM3 and SRAM4 memories clock enable */
		LL_MEM_EnableClock(LL_MEM_AXISRAM3);
		LL_MEM_EnableClock(LL_MEM_AXISRAM4);

		/* Power On AXSRAM3 and AXISRAM4 */
		hramcfg.Instance = RAMCFG_SRAM3_AXI;
		HAL_RAMCFG_EnableAXISRAM(&hramcfg);

		hramcfg.Instance = RAMCFG_SRAM4_AXI;
		HAL_RAMCFG_EnableAXISRAM(&hramcfg);

		__HAL_RCC_RIFSC_CLK_ENABLE();

		RIMC_master.MasterCID = RIF_CID_1;
		RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV;

		HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_DCMIPP,
		 &RIMC_master);
		HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_DCMIPP,
		RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
		/* USER CODE END DCMIPP_MspInit 1 */

	}

}
int main(void)
{

	......

	ret = Camera_Init();
	if (ret != 0) {
		printf("[ ERROR ] Camera init failed, error = %ld\n", ret);
		Error_Handler();
	}

	ret = HAL_DCMIPP_CSI_PIPE_Start(&hdcmipp, DCMIPP_PIPE0,
	DCMIPP_VIRTUAL_CHANNEL0, BUFFER_ADDRESS, DCMIPP_MODE_CONTINUOUS);
	if (ret != 0) {
		printf("[ ERROR ] DCMIPP PIPE0 start failed, error = %ld\n", ret);
		Error_Handler();
	}

	ret = Camera_Set_Format(FRAME_WIDTH, FRAME_HEIGHT);
	if (ret != 0) {
		printf("[ ERROR ] Camera set format, error = %ld\n", ret);
		Error_Handler();
	}

	......

}

There are some logs about DCMIPP and CSI state.

[ INFO ] DCMIPP state 2
[ INFO ] DCMIPP PIPE0 state 2
[ INFO ] DCMIPP error state 0x00000000
[ INFO ] DCMIPP_CMCR 0x00000001
[ INFO ] DCMIPP_CMFRCR 0x00000000
[ INFO ] DCMIPP_CMIER 0x00008620
[ INFO ] DCMIPP_CMSR1 0x00000003
[ INFO ] DCMIPP_CMSR2 0x00000000
[ INFO ] DCMIPP_P0FSCR 0x80030000
[ INFO ] DCMIPP_P0FCTCR 0x00000008
[ INFO ] DCMIPP_P0DCCNTR 0x00000000
[ INFO ] DCMIPP_P0PPCR 0x00000000
[ INFO ] DCMIPP_P0PPM0AR1 0x34200000
[ INFO ] DCMIPP_P0IER 0x00000000
[ INFO ] DCMIPP_P0SR 0x00000000
[ INFO ] DCMIPP_P0CFSCR 0x00030000
[ INFO ] DCMIPP_P0CFCTCR 0x00000008
[ INFO ] DCMIPP_P0CPPCR 0x00000000
[ INFO ] DCMIPP_P0CPPM0AR1 0x34200000
[ INFO ] CSI_CR 0x00000001
[ INFO ] CSI_PCR 0x0000000F
[ INFO ] CSI_IER0 0x58211100
[ INFO ] CSI_IER1 0x00001F1F
[ INFO ] CSI_SR0 0x06000000
[ INFO ] CSI_SR1 0xE4510000
[ INFO ] CSI_SPDFR 0x00000000
[ INFO ] CSI_ERR1 0x00000300
[ INFO ] CSI_ERR2 0x00000000
[ INFO ] CSI_PRCR 0x00000002
[ INFO ] CSI_PMCR 0x00000000
[ INFO ] CSI_PFCR 0x00010928

 

Thank you for your time and suggestions.

2 replies

ST Employee
September 8, 2025

Hello,

For Pixel Packer format youshould use DCMIPP_PIXEL_PACKER_FORMAT_YUV422_1_UYVY for "UYVY"

For DCMIPP and CSI clock configuration please refer to the applications on DK:

STM32CubeN6/Projects/STM32N6570-DK/Applications/DCMIPP at main · STMicroelectronics/STM32CubeN6 · GitHub

Best Regards,

 

Visitor II
July 29, 2026

Hi all,

I'm hitting what looks like the exact same issue described in this thread — STM32N6570-DK, IMX335 (MB1854B module), DCMIPP never delivers a completed frame despite the sensor being confirmed alive and streaming. I've traced it further than what's described above and want to share the specific failure point in case it helps pin down the root cause (or in case someone recognizes it immediately).

Setup: Custom FreeRTOS-based project (CMake toolchain via VS Code + STM32 extension), TrustZone Secure-only (AppS only, no AppNS split), external PSRAM (APS256XX via XSPI1) for frame buffers, using Camera_Middleware/CMW_CAMERA_* for sensor + DCMIPP setup rather than CubeMX-generated init.

Confirmed working (via debugger, so genuinely verified, not assumed):

  • IMX335 detected and probed successfully over I2C — CMW_CAMERA_Init() returns the sensor's real native resolution (2592×1944), not a stale/default value
  • Sensor streaming-start command (Camera_Drv.Start()) returns success
  • DCMIPP peripheral itself reports HAL_DCMIPP_STATE_READY
  • Pipe1's own state reports HAL_DCMIPP_PIPE_STATE_READY after configuration
  • CSI config matches ST's official DCMIPP_ContinuousMode example exactly: NumberOfLanes = DCMIPP_CSI_TWO_DATA_LANES, PHYBitrate = DCMIPP_CSI_PHY_BT_1600, DataTypeIDA/IDB = DCMIPP_DT_RAW10, VC DataTypeFormat = DCMIPP_CSI_DT_BPP10
  • RIF: RIF_MASTER_INDEX_DCMIPP set to RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV
  • Only one DCMIPP_HandleTypeDef instance exists/inits the peripheral (removed a redundant CubeMX-generated MX_DCMIPP_Init() that was double-initializing against a second handle)

Exact failure point: HAL_DCMIPP_CSI_PIPE_Start() → internal static DCMIPP_CSI_SetVCConfig() → after:

SET_BIT(csi_instance->CR, CSI_CR_VC0START);

it polls:

} while ((csi_instance->SR0 & (CSI_SR0_VC0STATEF << VirtualChannel)) != (CSI_SR0_VC0STATEF << VirtualChannel));

and this times out (DCMIPP_TIMEOUT ms) — VC0STATEF never sets, so HAL_DCMIPP_CSI_PIPE_Start() returns HAL_ERROR (CMW_ERROR_PERIPH_FAILURE at the CMW_CAMERA_Start() level).

Questions:

  1. Is there a known prerequisite before issuing VC0START that isn't captured in the standard HAL call sequence (e.g., a D-PHY calibration/training completion check, or a specific CSI reset sequencing step)?
  2. Is there a known RIF/CID attribute requirement specifically for the CSI host (as opposed to the DCMIPP master), given this is a TrustZone Secure-only build?
  3. Any known erratum around VC0STATEF on cold start, or interaction with external PSRAM (XSPI1) init happening before DCMIPP configuration?

Happy to share the full project/config if useful. Thanks in advance for any pointers.