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Hi ST Support Team,              I am Yashwanth Melwanki, Associated with Quest-Global as Technical Architect.               In one of designs [WIP], we are considering NUCLEO-H755ZI-Q and have connected below Peripherals placed on seperate board. connection is through MROPH headers CN11 and CN12.               All these peripherals will be active and set to run at max speed to the interfaces they are conencted to STM [I2C / SPI / USB / eMMS etc]              I wish to know, What is capacibility of STM32 to run and interact with these peripharals engaged at max speed?                             1. x1 USB FS to USB hub controller              2. x1 I2c to 2 GPIO expanders (24 bit each - one as GPO and Anlother as GPI)              3. x1 I2C to 1 GPIO expander, dedicated as 24Bit GPI              4. x1 Ethernet              5. x2 SPI: One for DAC (16bit, 16 Channel) interface and Another for ADC (16bit, 16 Channel) interface              6. x1 QSPI              7. x2 I2S; One as Inout a

I am using the ST67W611 Wi-Fi module with the ST67 W6X SDK to implement an HTTP web server.While profiling the performance, I observed that every call to W6X_Net_Send() takes approximately 391 ms (or more) regardless of the amount of data being transmitted. Test SetupModule: ST67W611 Interface: SPI Transport: TCP Firmware: 1.1.1 SDK Version : 2.0.89 MCU: STM32F4  QuestionsIs a fixed delay of approximately 391 ms per W6X_Net_Send() call expected? Is W6X_Net_Send() internally waiting for a TCP ACK or another event before returning? Is there any configurable transmit timeout or buffering mechanism that affects this behavior? Is there a recommended maximum chunk size for W6X_Net_Send() to improve throughput? Are there any SDK or firmware settings that can reduce this latency?Any guidance would be greatly appreciated.Thank you.

 Hi， the rear background exceeds 2 meters, and there are no obstacles in front of the sensor. The measurement data is unstable, and the reading sometimes reaches 0 and sometimes reaches 115.      

Hi all,disclaimer: I used AI to translate my question to english:I'm designing the power supply for a solar-charged, battery-powered outdoor device (wildlife camera controller) built around an STM32L476VG. I'd appreciate a sanity check of the architecture and the regulator choices.System:Input: 2S Li-Ion (NP-F pack), 6.0–8.4 V, reverse protection via P-FET MCU in STOP2 most of the time (target sleep budget: < 10 µA for the whole board) Always-on: MCU, RTC (AB1805), I2C EEPROM, a µA-class wake-up receiver Switched loads (active phases only, seconds to minutes): LoRa module (TX approx 120 mA), SD card (write bursts approx 100 mA), OLED, GPS Separate 5 V rail (TPS62147, EN-gated) for a Raspberry Pi that wakes for uploadsCurrent design: one 3.3 V rail from an MCP1703A (2 µA IQ, 250 mA), all loads behind individual load switches (TPS22919 etc.).Concern: worst-case concurrency (LoRa TX + SD write + MCU + OLED) sums to approx 250 mA -right at the LDO's limit, and (8.4 − 3.3 V) × 0.25 A app

Hi,I’m using TESEO-VIC3D for PPS generation for time synchronization and OCXO frequency correction. I wanted to use PSTMPPSDATA NMEA messages in order to read quantization_error parameter and apply it in my program to eliminate the quantization error of PPS signal. Mostly it works well, but I ran into couple of issues:There is a ref_sec parameter in the PSTMPPSDATA message that should refer to a specific second for which the message corresponds. For some seconds, this message is missing, e.g.:2026-07-11 17:43:09.564 $PSTMPPSDATA,1,1,1,0,0,0,0.500000,0,633,420,420,633,0,0,0,0,0,11,3,5,18,4,0,0,6.622e-09,65473709.68,48000018.67,4*242026-07-11 17:43:09.567 $PSTMTRAIMSTATUS,1,0,15,7,5,2,11*542026-07-11 17:43:09.573 $PSTMTRAIMUSED,1,5,7,21,11,16,9*7C2026-07-11 17:43:09.576 $PSTMTRAIMRES,1,5,-3,-9,6,-3,10*162026-07-11 17:43:09.580 $PSTMTRAIMREMOVED,1,2,30,4*2F2026-07-11 17:43:10.616 $PSTMTRAIMSTATUS,1,0,15,8,5,2,12*582026-07-11 17:43:10.620 $PSTMTRAIMUSED,1,5,7,21,11,16,9*7C2026-07-11 17:43:

The errata sheet for the STM32U585 (ES0499) is no longer listed in the documentation section on the product page, and the old download link now returns a 404 error. For reference, the following post includes a download link for ES0499 that no longer works. https://www.st.com/resource/en/errata_sheet/es0499-stm32u575xx-and-stm32u585xx-device-errata-stmicroelectronics.pdf How can this document be retrieved?  Thanks,Owen

Are there any single MCU + LoRa 2.4 GHz ICs in the world?

I used STM32F103 in a mix configuration of bare-metal&HAL supplied by STM32CubeMX. I'm not sure ST can provide the documentation that can be referenced to generate the SBOM for cybersecurity purpose. Is there any recommended tool to scan the firmware project folder. If ST is yet to provide a way to auto-generate SBOM for cybersecurity requirement, possible to use manually curated SPDX-based JSON format for machine processing. If anyone had gone through similar process for regulatory review, can you please share the experience? Any inputs/advise would be greatly appreciated. Thank you.

In the stm32 cubeMX Board selector menu I cant find board MKI-109D.How can I develop the board firmware? 

Hello, we are testing using an STM32H7R7L8H6 paired with an IS42S32800L-6BL. There are no data failures at 100MHz, but data failures occur after prolonged execution at 150MHz. What is the maximum FMC execution speed of the STM32H7R7L8H6? This test was conducted with the MCU DVDD pin unconnected. Is this related to the DVDD pin connection?

Hello,I am debugging USB function on STM NUCLEO-H723ZG demo board. I set the USB_DEVICE Mode as CDC(Virtual Port) mode. USB_OTG_HS can as below.Now I can get the virtual port number on the computer. But the VBUS over current LED (LD7) is always on. It indicates the VBUS over current. But I have configured the EN pin of STMPS2141STR as high (Set PD10/USB_FS_PWR_EN) to disable this fault. Can anyone please help to check what’s the problem? Thanks, 

Setup  - MCU: STM32U595VITxQ (Cortex-M33)  - ADC: ADC4, 57Mhz，12-bit, 7 channels, 6400 Hz sample rate, triggered by TIM1  - Data path: GPDMA1 in linked-list circular mode, double-buffered with half/complete callbacks (128 samples per half-buffer). DMA writes directly into a static INT16U s_adc4_result[256][7] buffer in normal SRAM.  - Signal chain: external current/voltage sensors → signal conditioning board (op-amps, anti-alias filter, DC bias) → ADC4 input pins  - Firmware: FreeRTOS, half-callback copies 128 samples per channel into a ring buffer (PF_TOTAL_WAVE_NUM = 40 slots × 128 samples), pf_task consumes from queue  Symptom  Most of time, everything works fine. But some times something wrong happened，in a log file we captured, channels simultaneously read byte-identical constant values.Questions:  1. Has anyone seen an STM32U5 ADC report "healthy" (no OVR, no error, ADSTART set) while consistently delivering a constant code per channel? Are there silicon errata I should check?  2

I spent a lot of time designing a prototype using the STM32H573MIY3Q, but now it’s out of stock (DigiKey/Mouser/JLC) and 78 week lead time (available Jan 1, 2028). I’m kicking myself for not asking earlier about STM’s commitment to this part.How do we get samples now? I guess I can go to the scalpers...But then is it even smart to design this into a product? What is STM’s planned production ramp?Initially I’ll sell a few hundred units but if it goes well I might need 10K+ per year.Am I delusional in hoping for the possibility?I apologize for my tone of frustration, but SEVENTY EIGHT WEEK lead time is hard to believe, and upsetting. Is this not a flagship microcontroller (STM32H5) and flagship package (WLCSP-80)?

Hi everyone,I'm working with the STM32F446RE and exploring the 6-step BLDC motor control example provided by the STM32 Motor Control SDK. In the CubeMX configuration of the firmware:3 GPIOs are configured as analog inputs:M1_BEMF_U → PC3 → ADC1_IN13M1_BEMF_V → PA7 → ADC1_IN7M1_BEMF_W → PB0 → ADC1_IN8However, in the ADC Injected Conversion Mode, only Channel 13 (PC3) is selected and used (1 injected conversion configured).See image below for reference:My question is:Why are all 3 BEMF pins configured in CubeMX if only Channel 13 is used in the ADC injected group?I expected that all 3 channels would be used in the injected sequence to sample U, V, and W BEMF voltages.Do they dynamically change the injected channel in code depending on the commutation step? Or is there another reason for this configuration?Thanks in advance for any clarification!

Hello Team,I have used STM6824SWY6F Part in one of my Design and I’m performing a de-rating analysis, so could you please share the below details,1. Junction Temperature2. Junction-to Ambient Thermal resistance3. Junction-to-case Thermal resistance4. Maximum power dissipationThanks,Deva

Hi everyone,I'm designing a custom development board based on the STM32H750XBH6 and originally planned to use the ISSI IS42S32400F-6BL (128 Mbit, 4M × 32, SDR SDRAM, 166 MHz, 90-ball BGA).However, this part appears to be obsolete/end-of-life, and availability is becoming an issue.I'm looking for recommendations for a newer SDRAM that is:Fully compatible (or requires minimal hardware/software changes) 128 Mbit or larger 32-bit data bus 3.3 V SDR SDRAM 166 MHz (or higher) 90-ball BGA (preferred) Currently in production and readily available from major distributorsHas anyone recently designed an STM32H750/H743 board and selected a newer SDRAM instead of the IS42S32400F-6BL?I'd appreciate recommendations for specific part numbers that are currently in production and known to work well with the STM32 FMC interface.Thanks in advance!

I want the motor to run at 4000pps with 38 V power supply and full step with 17HS 8401!In this case, which is superior, L6470 (voltage control) or L6472 (current control)? Also, if you have any points to keep in mind, please let me know.

Hi everyone,I'm working on an STM32H743-based product that already has a custom bootloader and I'm looking for the best industry practice for implementing a bootloader fallback mechanism.Current architecture0x08000000 Primary Bootloader0x08020000 Factory Application0x08080000 Default ApplicationThe bootloader already performs:Application validity checks (MSP and Reset Handler) CRC verification of the Factory and Default applications UART firmware update Automatic fallback from Default Application to Factory ApplicationThe applications are working as expected.New requirementThe new requirement is that if the primary bootloader becomes corrupted, the system should be able to boot from a backup bootloader stored elsewhere in flash, without requiring physical access (the device is remotely deployed).I understand that after reset the Cortex-M7 hardware simply does:MSP = *(0x08000000)PC = *(0x08000004)and immediately jumps to the Reset_Handler.My understanding is:If the vector table or R

Hello,At present I trt o interface an SPI based SSD1309 Display and I2C based DS3231 RTC with STM32F103RBT6 using Nucleo board MB1136 F103RB C. For your reference I have attached screenshot of port assignment for those devices.  void Init_GPIOs(void) {/* --- 1. Peripheral Clock Enable --- */// Enable clocks for all GPIO ports and AFIO (Alternate Function I/O)RCC->APB2ENR |= (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN |RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN |RCC_APB2ENR_AFIOEN); /* --- 2. Pin Remapping & JTAG Management --- */// Disable JTAG/SWD remap to reclaim PB3, PB4, and PA15 for GPIO/Alternate Function usageAFIO->MAPR &= ~AFIO_MAPR_SWJ_CFG;AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_JTAGDISABLE;// Remap SPI1 to PB3/PB4/PB5 as per hardware designAFIO->MAPR |= AFIO_MAPR_SPI1_REMAP; /* --- 3. Initialize Display Control Pins (Soft-Step) --- */// Configuring critical control pins first ensures the display state is stable// before the high-speed SPI clock begins toggling.GPIOB-&gt

Hi ST, Actually , In my Correct Project, i need Small SIZE PCB , So there is no left space in my PCB , So can i replace this PMIC to another PMIC which is in small Size, please Suggest me Any PMIC which is compatible with MP257, 

I have created a project and none of the options on my screen seem to do anything. All im trying to do is compile a simple code on STM32CubeIDE and flash a board using the STM32CubePRG software. 

Create a new project on macOS using STM32CubeIDE for VSCode.In the CMakeLists.txt file, add:add_link_options(-flto=auto -ffat-lto-objects)Build the project.You should get a linker error like this, because GNU Tools for STM32 is located in the “Application Support” folder which contains a space, so lto-wrapper can’t manage to access its dependencies:[build] Linking C executable core_mcu_firmware.elf[build] make[3]: /Users/romain/Library/Application: Permission denied[build] make[3]: /Users/romain/Library/Application: Permission denied[build] make[3]: *** [/var/folders/hb/49ldjdz961l9dtpyqq8dqhcr0000gn/T//ccLALceE.ltrans1.ltrans.o] Error 1[build] make[3]: *** Waiting for unfinished jobs....[build] make[3]: *** [/var/folders/hb/49ldjdz961l9dtpyqq8dqhcr0000gn/T//ccLALceE.ltrans0.ltrans.o] Error 1[build] lto-wrapper: fatal error: make returned 2 exit status[build] compilation terminated.[build] /Users/romain/Library/Application Support/stm32cube/bundles/gnu-tools-for-stm32/14.3.1+st.2/bin/.

HardwareBoard: NUCLEO‑U5A5ZJ‑QMCU: STM32U5A5ST‑LINKSoftware / ToolsST Edge AI (via STM32CubeAI Studio)Target: STM32U5Model source: STM32 AI Model ZooModel used:miniresnetv2_s1_64x50_tl_int8.tflite(Audio Event Classification → ESC‑10)Steps FollowedImported the miniresnetv2_s1_64x50_tl_int8.tflite model into STM32CubeAI StudioSelected NUCLEO‑U5A5ZJ‑Q as the target boardKept default settings in all stepsRun on Target Generated code, built, flashed, and attempted (Step 4 – Validate) failed Observed IssueDuring Run on Target, validation fails with the following error:Run failed: Error: validate error: E200 (ValidationError): TARGET: Unable to bind the ST.AI runtime with "network" c-model E801 (HwIOError): Invalid firmware - COM8:115200I have attached the complete validation failure log for reference.Additional ObservationDuring Step 1 (Code Generation), I consistently receive the following warning from STM32CubeMX:Warning: Code GenerationMain Config: These peripherals still have some n

Dear STM32 Technical Team:Our original design is implemented on the STM32F407, utilizing a single ADC pin for analog signal acquisition. Upon detection of a key trigger signal, high-speed data acquisition is performed via TIM1-triggered ADC1 with DMA transmission, where Analog Watchdog 1 is configured with Threshold A for boundary supervision. In the idle state without a key trigger, TIM2-triggered ADC2 operates in background mode with Analog Watchdog 2 (Threshold B) to continuously monitor abnormal signal fluctuations in real time.Due to the limited on-chip RAM of the STM32F407, we have migrated the firmware to the STM32L4S5 microcontroller. However, this device only features a single ADC peripheral, which prevents the independent dual-ADC operation implemented in the original design. Furthermore, although the STM32L4S5 integrates three analog watchdogs, the hardware does not support configuration of independent threshold levels for separate operational modes.We kindly request your of

I’ve noticced recently that in CubeIDE 2.x, the MXCube program was separated from CubeIDE and is now a standalone app. I’ve also noticed that the extensions download a more recent C standard for STM32 compiler and MCUFinder is now web-only. This to me signifies a pivot in where STM is going with development environment and my guess is that everything will focus on VSCode extensions. Having said that, I’m inclined to port my whole project in VSCode but I want some reassurance that the platform and its MCUs will get future enhanced support for VSCode extensions and better integration.So far, CMake scrips in VSConde aren’t fully fledged, specifically missing out-of-the-box commands and buttons for:- Switching active configuration (Debug or Release)- Flashing the target MCU.- Debugging via line-by-line walkthroughs.- Set debug levels and optimisations.- Set hardware or software floating points.- Output .bin firmwareMy question is. Is this the case and is better for me to port everything to