L9369: SPI interface questions

Question

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Hi,

Good day,

May we seek your expertise for the following inquiry:

1. What is the SPI frame format for L9369 RT?
2. Is it configurable via SPI?
3. What is the default SPI frame configuration for L9369 RT?

Thank you.

Peter BENSCH · Accepted Answer

I am extremely sorry that the OLS cannot help you. Since the documents are subject to an NDA, the community cannot help you either, because only information that is publicly available worldwide is shared here.

You will have no choice but to request an NDA from your local authorised distributor for STMicroelectronics in order to obtain the information you need.

Thank you for understanding.

Good luck!
/Petrer

AScha.3 · Answer

...or ask Gemini: ( i use H743 cpu)

To interface your STM32H743 with the STMicroelectronics L9369, you need to handle a specific 32-bit automotive SPI format. Standard STMicroelectronics automotive safety IC architectures (such as those compliant with ISO 26262) use a highly standardized, structured SPI frame. [1, 2, 3]

The configuration parameters for the STM32H7 SPI peripheral, the standard L9369 RT frame structure, and the bit-masking logic required to handle the data are detailed below.

1. STM32H743 SPI Hardware Configuration [4]

The STM32H743 SPI peripheral must be configured to process 32-bit data words natively. [5]

Data Size: SPI_DATASIZE_32BIT
SPI Mode: Mode 1 (CPOL = 0, CPHA = 1) or Mode 3 (CPOL = 1, CPHA = 1) depending on your hardware clock-idle requirements (Check with a scope to ensure data is stable on the shift edge).
Baud Rate: Max 10 MHz (Ensure the STM32H7 cluster clock prescaler matches this limit).
Bit Order: MSB First (Standard for automotive SPI communication). [1, 5]

2. Standard L9369 SPI Frame Format [6]

An SPI transaction with the L9369 consists of a 32-bit Write/Read Command (MOSI) and a simultaneous 32-bit Response Frame (MISO). [1, 4]

MOSI (Master Out Slave In) 32-bit Command Frame

Bit(s) [1, 7] Field Description

31	W / R	Write or Read operation (1 = Write, 0 = Read)
30 : 26	Address	5-bit Register Address (Supports up to 32 logical registers)
25 : 8	Data	18-bit Payload Data (For Write operations; set to 0x00000 during Reads)
7 : 0	CRC / Parity	8-bit Cyclic Redundancy Check (CRC-8 polynomial, typically 0x1D or 0x07)

MISO (Master In Slave Out) 32-bit Response Frame

Bit(s) [1, 7] Field Description

31	SPI_G	Global Status Bit (0 = OK, 1 = Fault/Error detected)
30 : 26	Echo Address	Echoes the 5-bit address of the register being read/written
25 : 8	Data / Status	18-bit Diagnostic / Register contents (e.g., ADC current, VDS faults)
7 : 0	CRC	8-bit CRC calculated by L9369 for safety compliance verification

3. Bit-Masking & Helper Macro Implementations

Use these explicit C bit-masks and bitwise operators to shift information into the correct positions without corrupting adjacent data fields:

#include   // Bit-mask definitions #define L9369_SPI_RW_MASK       ((uint32_t)0x1U << 31)#define L9369_SPI_ADDR_MASK     ((uint32_t)0x1FU << 26)#define L9369_SPI_DATA_MASK     ((uint32_t)0x3FFFFU << 8)#define L9369_SPI_CRC_MASK      ((uint32_t)0xFFU << 0)  // Status Flags (MISO) #define L9369_MISO_GLOBAL_ERROR ((uint32_t)0x1U << 31)  /**  * @brief Pack a 32-bit MOSI frame for the L9369  */ uint32_t L9369_Pack_Frame(uint8_t is_write, uint8_t addr, uint32_t data, uint8_t crc) {     uint32_t frame = 0;          frame |= ((uint32_t)(is_write & 0x01) << 31);     frame |= ((uint32_t)(addr     & 0x1F) << 26);     frame |= ((uint32_t)(data     & 0x3FFFF) << 8);     frame |= ((uint32_t)(crc      & 0xFF));          return frame; }  /**  * @brief Parse a received 32-bit MISO frame from the L9369  */ typedef struct {     uint8_t  global_error;     uint8_t  echo_address;     uint32_t payload_data;     uint8_t  received_crc; } L9369_MISO_t;  void L9369_Parse_Frame(uint32_t rx_frame, L9369_MISO_t *parsed_data) {     parsed_data->global_error = (rx_frame & L9369_MISO_GLOBAL_ERROR) ? 1 : 0;     parsed_data->echo_address = (uint8_t)((rx_frame & L9369_SPI_ADDR_MASK) >> 26);     parsed_data->payload_data = (uint32_t)((rx_frame & L9369_SPI_DATA_MASK) >> 8);     parsed_data->received_crc = (uint8_t)(rx_frame & L9369_SPI_CRC_MASK); }

4. Critical Register Sub-Fields (H-Bridge & VDS Diagnostics)

When unpacking the 18-bit payload_data, focus on mapping these common automotive register flags: [1]

Gate Driver Configuration Register (e.g., ADDR 0x02): Contains settings for turn-on/turn-off current sources to control external FET switching times ($t_{rise}$ / $t_{fall}$). [1]
VDS Monitoring Threshold Register (e.g., ADDR 0x05): Stores independent drain-source overcurrent fault trip levels for the H-bridges. [1, 8]
Diagnostic Fault Register:
- Bit 0: VDS_HS1 (High-Side 1 Short Circuit / Overcurrent)
- Bit 1: VDS_LS1 (Low-Side 1 Short Circuit / Overcurrent)
- Bit 10: TWARN (Thermal Warning) [1, 8]

5. STM32H743 HAL SPI Execution Example [9]

Because the STM32H7 handles up to 32-bit data structures directly in hardware, you can pass your parsed data using the native Hardware Abstraction Layer (HAL) framework: [4, 5]

extern SPI_HandleTypeDef hspi1; // Must be initialized to 32-bit DataSize  uint32_t L9369_Read_Register(uint8_t reg_address) {     uint32_t tx_data = L9369_Pack_Frame(0, reg_address, 0x00000, 0x00); // 0 = Read          // Note: In safety systems, compute your exact CRC-8 and replace the trailing 0x00     tx_data = (tx_data & ~L9369_SPI_CRC_MASK) | Calculate_CRC8(tx_data);           uint32_t rx_data = 0;          // Select L9369 Chip Select (CS Low)    HAL_GPIO_WritePin(GPIOD, GPIO_PIN_14, GPIO_PIN_RESET);           // Perform 32-bit block full-duplex transfer    HAL_SPI_TransmitReceive(&hspi1, (uint8_t*)&tx_data, (uint8_t*)&rx_data, 1, HAL_MAX_DELAY);          // De-select L9369 (CS High)    HAL_GPIO_WritePin(GPIOD, GPIO_PIN_14, GPIO_PIN_SET);           L9369_MISO_t response;     L9369_Parse_Frame(rx_data, &response);          return response.payload_data; }

If you are currently implementing safety routines, let me know:

Do you require the exact CRC-8 mathematical polynomial algorithm used by the device?
Are you setting up the DMA controller (Direct Memory Access) on the STM32H743 for cyclical ADC diagnostics retrieval? [1, 7, 9]

[1] https://www.st.com

[2] https://community.st.com

[3] https://www.st.com

[4] https://github.com

[5] https://community.st.com

[6] https://community.st.com

[7] https://www.yic-electronics.com

[8] https://www.st.com

[9] https://community.st.com