The function LL_PLL_ConfigSystemClock_HSI() in stm32g4xx_ll_utils.c temporarily divides the AHB clock by 2 if the SYSCLK divider is 1. According to the comments, this is to "Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2".
The issue is that during this temporary AHB clock rate, the SystemCoreClock is updated to also be 1/2 the expected clock.
Although LL_PLL_ConfigSystemClock_HSI() resets the AHB clock properly, it does not reset the global variable SystemCoreClock.
This incorrect value is exposed when trying to set the UART baud rate later on in stm32g4xx_hal_uart.c.
Note that I'm using the latest from https://github.com/STMicroelectronics/STM32CubeG4 (0f8a4fd) with this recent pull-request integrated.
The following patch fixes the issue. Is this the correct solution? If so, I'm happy to issue a PR.. but do not know where to do it as there is conflicting info across the web.
diff --git a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c
index ea78949a..49bdac0c 100644
--- a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c
+++ b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c
@@ -329,6 +329,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS
{
UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_SetSystemCoreClock(pllfreq);
}
}
else
