STM32L476: OTG_FS: IN endpoint FIFOx transmit RAM start address is word address or byte address aligned to 32-bit memory location

[MSuhe]

Can someone please clarify if the IN endpoint FIFOx transmit RAM start address part of OTG_DIEPTXFx register should be "word address" or "byte address aligned to 32-bit boundary".

We are currently treating this as "word address", inline with what STM32CubeMx does and also libopencm3 USB stack. But, we are having some issues with FIFO corruption and suspect IN endpoint FIFOx transmit RAM start address is not "word address" as it is not explicitly specified as word address anywhere else in reference manual.

I have also attached the snapshot of the register description from STM32L476 reference manual can someone please confirm what is correct?

[waclawek.jan]

Every FIFO-related value in the OTG registers is in 32-bit words, i.e. the address is word address (byte address / 4).

JW

[MSuhe]

Thanks for your response. Your statement is valid for STM32F411 OTG_FS as well ?

[MSuhe]

Thanks for your response. Just for experimental purpose, we tried setting the TX FIFO RAM start address as "byte address" as below:

RX FIFO: only FIFO depth in words

-------------------------

OTG_GRXFSIZ.RXFD[15:0]: Rx FIFO depth = 0x80 (128 32-bit words for RX FIFO).

TX FIFO 0: EP 0 (FIFO depth in words & FIFO start address in bytes)

-------------------------

OTG_DIEPTXF0 = 0x0040 0200 (Depth of 64 (0x40) words & RAM start address in bytes 0x200). Immediately below RX FIFO.

TX FIFO 1: EP 1(FIFO depth in words & FIFO start address in bytes)

-------------------------

OTG_DIEPTXF1 = 0x0040 0300 (Depth of 64 (0x40) words & RAM start address in bytes 0x300). Immediately below TX FIFO 0.

Now, STM32L476 only has 1.25Kbytes (1280 bytes = 320d (0x140) words) of RAM for HW FIFO. As there are only 0x140 words of RAM available

FIFO start address as above for EP0 & EP1 is invalid (or out of range). But, USB communication seems to work fine.

How does one conclude, that FIFO addresses as shared above are wrong? Because USB communication seems to work.

If the addresses are totally invalid, shouldn't it just crash or fail to communicate of IN endpoint 1 ?

Can you please share your inputs.

[MSuhe]

Hi Jan,

Can you please share your inputs to above queries.

Regards,

Suhel

[waclawek.jan · Accepted solution]

> If the addresses are totally invalid, shouldn't it just crash or fail to communicate of IN endpoint 1 ?

I don't know how does the HW behave when you misconfigure it. It may quite well simply ignore the highermost bits. That would make your EP0 Rx buffer to be at word address 0x000, the same as the Tx buffer. If Rx and Tx don't overlap in time - which is often the case for EP0 - then the FIFO buffers can overlap and everything would seemingly work.

> Your statement is valid for STM32F411 OTG_FS as well ?

Yes, it's the same Synopsys DWC2 OTG IP. There are subtle differences as different versions of the IP are used, but this is a major feature so it's the same.

JW

[MSuhe]

Thanks a lot for your inputs.