STM32H7 FDCAN classic can Tx complete interrupt is missed when messages are being received

[FMaso]

I have configured FDCAN for classic CAN frame in STM32CubeIDE with Firmware package version 1.9.1. Following is my configuration:

hfdcan1.Instance = FDCAN1;
  hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
  hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
  hfdcan1.Init.AutoRetransmission = DISABLE;
  hfdcan1.Init.TransmitPause = DISABLE;
  hfdcan1.Init.ProtocolException = ENABLE;
  hfdcan1.Init.NominalPrescaler = 6;
  hfdcan1.Init.NominalSyncJumpWidth = 1;
  hfdcan1.Init.NominalTimeSeg1 = 13;
  hfdcan1.Init.NominalTimeSeg2 = 2;
  hfdcan1.Init.DataPrescaler = 6;
  hfdcan1.Init.DataSyncJumpWidth = 1;
  hfdcan1.Init.DataTimeSeg1 = 13;
  hfdcan1.Init.DataTimeSeg2 = 2;
  hfdcan1.Init.MessageRAMOffset = 0;
  hfdcan1.Init.StdFiltersNbr = 0;
  hfdcan1.Init.ExtFiltersNbr = 0;
  hfdcan1.Init.RxFifo0ElmtsNbr = 32;
  hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
  hfdcan1.Init.RxFifo1ElmtsNbr = 0;
  hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
  hfdcan1.Init.RxBuffersNbr = 0;
  hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
  hfdcan1.Init.TxEventsNbr = 0;
  hfdcan1.Init.TxBuffersNbr = 0;
  hfdcan1.Init.TxFifoQueueElmtsNbr = 1;
  hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
  hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
  if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN FDCAN1_Init 2 */
 
  /* Start the FDCAN module */
  if (HAL_FDCAN_Start(&hfdcan1) != HAL_OK)
  {
    /* Start Error */
    Error_Handler();
  }
 
  if (HAL_FDCAN_ActivateNotification(&hfdcan1, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0x0) != HAL_OK)
  {
    /* Notification Error */
    Error_Handler();
  }
  if (HAL_FDCAN_ActivateNotification(&hfdcan1, FDCAN_IT_TX_COMPLETE | FDCAN_IT_TX_FIFO_EMPTY, 0xFFFFFFFF) != HAL_OK)
  {
 
	  Error_Handler();
 
  }
  /* USER CODE END FDCAN1_Init 2 */

I have tested that I can consistently get one Tx complete callback for every message sent when there are no messages being received. When I start receiving messages, the Tx complete callbacks are missed sometimes. Bus load is <60%.

[Tesla DeLorean]

ST doesn't do much real-world / use-case testing, expect you're going to have to pull out the manuals, inspect the peripheral registers, and walk/understand the code flow and behaviour.

Indicative or it stomping on, or missing/ignoring status flags and callback paths. Or that the callbacks themselves muddy the internal state.

Code provided "AS IS"

[FMaso]

I understand, but this is the first time I have used FDCAN, I am not very familiar with the architecture. Maybe some of the more experienced folks here could help point me in the right direction to walk the code flow. Thats what I was hoping. Thanks.

[FMaso · Accepted solution]

Ok, so I modified the original ISR code, moved Tx complete processing up before Rx processing, and that solved the problem.