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STM32H563: meaning of "PLL1" on STM32CubeMX clock tree?

aika_sanshin_fromjp
Associate

‎2024-11-07 12:51 AM - last edited on ‎2024-11-07 01:31 AM by

Does anyone know  what is the "PLL 1" parameter on STM32CubeMX clock tree?

I am using STM32H563 Nucleo board and found that there is "PLL1" parameter.

When I change this 0 to 1, SYSCLK was changed a little bit, 125 to 125.000122.

aika_sanshin_fromjp_1-1730968984755.png

aika_sanshin_fromjp_2-1730969103258.png

I would like to know why this change happen, and found the PLL1VCOSEL.

Is this bit relevant to the setting?

Let me know why the change happen and what register related to "PLL1".

aika_sanshin_fromjp_0-1730968887146.png

 

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Sarra.S
ST Employee

‎2024-11-07 01:10 AM - edited ‎2024-11-07 01:10 AM

Hello @aika_sanshin_fromjp, welcome to ST Community, 

This change is likely due to the fractional part of the PLL configuration. The relevant register for this setting is the RCC_PLL1FRACR (RCC PLL1 Fractional Divider Register, check section 11.8.11 in RM). The fractional part of the PLL configuration allows for fine-tuning of the output frequency, which can result in very small changes in the SYSCLK frequency.

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