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Project generation for STM32H7 with FreeRTOS + LwIP

heveskar
Senior

Hello,

I think there is a room for improvement in the cube when we create a project with LwIP and FreeRTOS. With the recent HAL update 1.10.0, whole ethernet driver changed and with it also the addresses where the buffers can be saved. With this our ethernet stop working, but we managed to fix it. I know there is an example in \STM32Cube\Repository\STM32Cube_FW_H7_V1.10.0\Projects\NUCLEO-H723ZG\Applications\LwIP\LwIP_HTTP_Server_Netconn_RTOS and I used it for the correct settings of the linker sections and MPU settings. However, in the generated ethernetif.c file there is missing this code:

#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma location = 0x30000400
extern u8_t memp_memory_RX_POOL_base[];
 
#elif defined ( __CC_ARM ) /* MDK ARM Compiler */
__attribute__((section(".Rx_PoolSection"))) extern u8_t memp_memory_RX_POOL_base[];
  
#elif defined ( __GNUC__ ) /* GNU Compiler */
__attribute__((section(".Rx_PoolSection"))) extern u8_t memp_memory_RX_POOL_base[];
  
#endif

for setting rx pool address. It took some time to debug this, but in ethernetif.c from the example, this code is there.

I think it should also be in the generated file from the cube, so that after setting all of the required things there, only code to edit is the linker file and then the code works out of the box.

Regards,

Karel

1 REPLY 1
Pavel A.
Evangelist III

On H7, addresses 0x3000xxxx belong to domain D2 where is the ETH module itself.

The D2 RAMs are not enabled on power-up.

It would be a good idea to enable the D2 RAM block in the same code section that allocates this memory for ETH use. IMHO will be clearer to understand and maintain.