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vchilapu
vchilapu
Associate II
June 24, 2022
Solved

STM32G474 discovery kit HRTIM ISR (HRTIM1_TIMA_IRQHandler) not hit for channel set Interrupt(SETx1) and channel reset interrupt(RSTx1).

  • June 24, 2022
  • 2 replies
  • 2774 views

Hi,

I have enabled the interrupts for channel set (SETx1) and channel reset (RSTx1) by setting bits RSTx1IE and SET1xIE. I am trying to drive the outputs to active-inactive state via software by writing to SST and RST bits of the TIMERA.

Inside the TIMAISR register I can see the SETx1 and RSTx1 interrupt event flags are set. This indicates the fact that output active-inactive state changes are driving the interrupts.

But I cannot see the respective ISR HRTIM1_TIMA_IRQHandler getting hit. While other interrupts are working fine and I can see the ISR gets executed in those situations, it is only for the SETx1 and RSTx1/SETx2 and RSTx2 I see this problem.

Is there any settings I could me missing that might cause this issue?

This topic has been closed for replies.
Best answer by Vincent Onde

Hi,

No, I meant that having RSTxIE and SETxIE set is not enough. The DIER register is duplicated , with a preload register (written by the CPU) and an active register (which actually controls the interrupt enable signal). To have the interrupt enabled, the content of the DIER_Preload must be transferred into the DIER_Active. There are multiple means to do this transfer (so called update), usually on counter roll-over. For a quick trial, you can force this update by software writing the TASWU bit in the HRTIM_CR2 register.

Best regards,

Vincent

2 replies

Vincent Onde
Vincent Onde
ST Employee
July 8, 2022

Hi,

Was the HRTIM_TIMADIER register updated after you've set the RSTxIE and SETxIE bits? This could explain the situation (interrupt enable bit set in preload register but not transferred into the active register). You can force an update without starting the timer with the TASWU bit in the HRTIM_CR2 register.

vchilapu
vchilapuAuthor
Associate II
July 12, 2022

Hi Vincent,

You mean to say the below bits?

They are indeed set.

0693W00000QKuw0QAD.jpgAlso, please note the below flags are set that tell interrupt occurred:

0693W00000QKuwKQAT.jpg 

Vincent Onde
Vincent OndeBest answer
ST Employee
July 12, 2022

Hi,

No, I meant that having RSTxIE and SETxIE set is not enough. The DIER register is duplicated , with a preload register (written by the CPU) and an active register (which actually controls the interrupt enable signal). To have the interrupt enabled, the content of the DIER_Preload must be transferred into the DIER_Active. There are multiple means to do this transfer (so called update), usually on counter roll-over. For a quick trial, you can force this update by software writing the TASWU bit in the HRTIM_CR2 register.

Best regards,

Vincent

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