ADC dual mode
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‎2024-10-09 6:19 PM
Hi i'm using MCU : STM32H743ZGT.
At several ADC documents, it says that when ADC1 and ADC2 end sampling, the two results are stored in ADC_CDR together.
The top 16 bits are the result of ADC2, or slave ADC, and the bottom 16 bits are the result of ADC1, or master ADC.
I want to know how the two ADCs are stored in different registers, for example, each ADC_DR.
Because I want to get more than 16 bits of data.
Of course, we use the two ADCs as dual mode.
Is there any other way?
Thank you.
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ADC
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STM32H7 series
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‎2024-10-11 9:29 AM
Hello @giwonKIM ,
According to the internal feedback, ADC values are also stored in ADC_DR register in DUAL mode for both ADCs.
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‎2024-10-10 8:48 AM - edited ‎2024-10-10 9:01 AM
Hello @giwonKIM ,
I'm checking internally and get back to you as soon as I have a feedback.
Internal ticket number for tracking 193439.
Thank you for your patience.
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‎2024-10-10 11:04 AM
I see in Reference manual RM0433 Rev 6, ADC section, p. 1029:
Bits 15:14 DAMDF[1:0]: Dual ADC Mode Data Format
This bit-field is set and cleared by software. It specifies the data format in the common data
register ADCx_CDR.
00: Dual ADC mode without data packing (ADCx_CDR and ADCx_CDR2 registers not used).
01: Reserved.
10: Data formatting mode for 32 down to 10-bit resolution
11: Data formatting mode for 8-bit resolution
Register: ADC x common control register (ADCx_CCR) (x=1/2 or 3)
Example: page 981
Interleaved dual mode: a DMA request is generated each time a new 32-bit data is
available:
1st DMA request: ADCx_CDR2[31:0] = MST_ADC_DR[31:0]
2nd DMA request: ADCx_CDR2[31:0] = SLV_ADC_DR[31:0]
And I see HAL can configure DAMDF bits:
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
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‎2024-10-11 9:29 AM
Hello @giwonKIM ,
According to the internal feedback, ADC values are also stored in ADC_DR register in DUAL mode for both ADCs.
