8MHZ HSE crystal. HSE selected and PLLCLK selected.
64MHZ / 115200 / 16 = 34.7222
Assuming the CPU picked 34 as the divisor then the baud rate is 117647.1 2% too high
But setting to 59MHz I was able to successfully communicated at 921,600
59MHZ / 921600 / 16 = 4.0012 (assuming divisor = 4 then 99.9702% accurate)
59MHZ / 115200 / 16 = 32.009 (assuming divisor = 32 then 99.9702% accurate)
What I'm asking for is in the IDE to show the UART Baud rate error, like the I2S device does as below.
from RM0454 Rev 3 Page771
The oversampling method can be selected by programming the OVER8 bit in the USART_CR1 register either to 16 or 8 times the baud rate clock (see Figure 267 and Figure 268).
Depending on your application:
• select oversampling by 8 (OVER8 = 1) to achieve higher speed (up to usart_ker_ck_pres/8). In this case the maximum receiver tolerance to clock deviation is reduced (refer to Section 26.5.8: Tolerance of the USART receiver to clock deviation on page 775)
• select oversampling by 16 (OVER8 = 0) to increase the tolerance of the receiver to clock deviations. In this case, the maximum speed is limited to maximum usart_ker_ck_pres/16 (where usart_ker_ck_pres is the USART input clock divided by a prescaler).
Thus @64MHz using 16x oversampling the maximum baud rate is 4MHz.
So 'ideally' if 16x oversampling, SYSCLK should be a 16x multiple of the baud rate.
or 'ideally' if 8x oversampling, SYSCLK should be a 8x multiple of the baud rate.
