H5 ADC clock

[MikeInMinnesota]

Hi, I'm using the Cube IDE 1.17 on an H5.  The HCLK is 248MHz.  When I try to configure the ADC/DAC clock to use HCLK, I get a red error.  According to the data sheet, the maximum clock to the ADC is 75MHz.  I am configuring the clock as divide by 6.

Am I misunderstanding the maximum ADC clock rate in the datasheet?  The part should be able to perform 5 MSPS.

Regards,

Mike 

[TDK]

There are limits on  f_adc_ker_ck_input, which is the clock fed to the ADC before it is divided down. The limit varies by part and by run mode.

There are additional limits on f_adc_ker_ck, which is the clock after it's been divided down.

[AScha.3]

Hi,

so choose a somewhat lower clock... (that can work on AHB bus)

+ the "red error" telling you, whats wrong (just go with mouse pointer at it).

If you clock it at 75M , it can reach 5 Msps / 12 bit. (with minimum sampling time)

But be aware: it needs low impedance driving the input then:

[MikeInMinnesota]

Hi, thanks for all the advice.

The part is an STM32H523CC.

The ADC portion of the clock tree is:

Hovering doesn't display any error message.

The main setup for the APBs is:

That's selecting HSI, PLLM/4, N=X31, P=/2 and PLL1P to SYSCLK

The ADC itself is independent, with no injected channels.  The HCLK is divided by 6 for the ADC, and sampling is 6.5+2.5=9 clocks.  That's a little under 5 MSPS.

Would I be better off using PLL2R to bring in the ADC clock, already divided by 6?

[SofLit · Accepted solution]

Hello @MikeInMinnesota 

Please refer to the datasheet:

At System clock of 248Mhz you are at VOS0. fADC ker clock should not exceed 125Mhz.

This is already shown by the message in CubeMx:

You can use PLL2 for the ADC kernel clock to not exceed 125Mhz at VOS0:

Example of ADC ker clk = 108Mhz keeping the system clock at 248Mhz.

Hope that answers your question.

[TDK]

> Would I be better off using PLL2R to bring in the ADC clock, already divided by 6?

Yes. That fixes the restriction on f_adc_ker_ck_input. Assuming f_adc_ker_ck can be 75 MHz at your run mode, it will work.

[MikeInMinnesota]

Hi, SofLit and TDK - thanks, that resolves it.

The bug in the CubeIDE is if the clock tree is reloaded then the error message of needing to be less than 125MHz does not display.  That's with version 1.17.

I guess was confused by the adc_ker_ck restriction to 125MHz and what clock was selected.  I thought by selecting HCLK in the CubeIDE then I'd get adc_hclk instead of adc_ker_ck_input.  Using adc_ker_ck_input means I should set CKMODE to 0 instead of adc_hclk/1.

Regards,

Mike