H5 ADC clock

MikeInMinnesota · ‎2025-02-12

Hi, I'm using the Cube IDE 1.17 on an H5. The HCLK is 248MHz. When I try to configure the ADC/DAC clock to use HCLK, I get a red error. According to the data sheet, the maximum clock to the ADC is 75MHz. I am configuring the clock as divide by 6.

Am I misunderstanding the maximum ADC clock rate in the datasheet? The part should be able to perform 5 MSPS.

Regards,

Mike

STTwo-32 · ‎2025-02-12

Hello @MikeInMinnesota @and welcome to the ST Community.

Could you please give me the exact part number of your MCU and a screenshot of your Clock tree and another one for the message you are receiving.

Best Regards.

STTwo-32

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TDK · ‎2025-02-12

There are limits on f_adc_ker_ck_input, which is the clock fed to the ADC before it is divided down. The limit varies by part and by run mode.

There are additional limits on f_adc_ker_ck, which is the clock after it's been divided down.

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AScha.3 · ‎2025-02-12

Hi,

so choose a somewhat lower clock... (that can work on AHB bus)

+ the "red error" telling you, whats wrong (just go with mouse pointer at it).

If you clock it at 75M , it can reach 5 Msps / 12 bit. (with minimum sampling time)

But be aware: it needs low impedance driving the input then:

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