Hi,
I am trying to minimise the error between the I2S sampling rate.
You can do this pretty well in the STM32F4 because it has an independent I2SPLL (0.02% error between target sampling rate and actual rate is excellent), this is done by changing the PLLI2S N and R values. However, I do not understand why the 48kHz sample rate needs "I2S clocks (MHz)" to be around 49 MHz. Can someone explain that?
