Hi, I'm using the Cube IDE 1.17 on an H5. The HCLK is 248MHz. When I try to configure the ADC/DAC clock to use HCLK, I get a red error. According to the data sheet, the maximum clock to the ADC is 75MHz. I am configuring the clock as divide by 6....
Hi, SofLit and TDK - thanks, that resolves it.The bug in the CubeIDE is if the clock tree is reloaded then the error message of needing to be less than 125MHz does not display. That's with version 1.17.I guess was confused by the adc_ker_ck restrict...
Hi, thanks for all the advice.The part is an STM32H523CC.The ADC portion of the clock tree is:Hovering doesn't display any error message.The main setup for the APBs is:That's selecting HSI, PLLM/4, N=X31, P=/2 and PLL1P to SYSCLKThe ADC itself is ind...
