1 ACCEPTED SOLUTION
Accepted Solutions
Even there is a u-boot sign on, the actual error occurs in tzc400.c in the OP-TEE code tree in the dump_fail_filter function . That was a bit misleading, I was assuming u-boot is running, and perhaps it is, but the memory access could be checked by OP-TEE code. not sure how this works but guess OPTEE is a "service" to u-boot
it is a PRIVILEGED write but a non-secure access. I interpreted that as that caller has right to access the memory area but not for write access. Perhaps that is a wrong conclusion.
it reports filter "0" , where can this filter be found ? what is AXI ID 480 ?
io_read32(tzc.base + FAIL_ID(filter))) = 480
EMSG("Violation @0x%"PRIx64", %ssecure %sprivileged %s, AXI ID %"PRIx32,
addr,
nonsecure_not_secure(filter) ? "non-" : "",
priv_not_unpriv(filter) ? "" : "un",
write_not_read(filter) ? "write" : "read",
io_read32(tzc.base + FAIL_ID(filter)));
There were issues about the location of the shared memory before:
https://github.com/OP-TEE/optee_os/issues/5275
ST TF-A v2.6 (e.g. tag v2.6-stm32mp-r1) and mainline OP-TEE don't comply on the location of the secure memory and reserved shared memory in DDR. ST TF-A v2.6-stm32mp-r1 locates the 2MB rsv shm below the 30MB secure DDR whereas mainliine OP-TEE (and mainline TF-A v2.6/v2.7) locates the rsv shm above the secure DDR area. Once consistent, boot is fine.
My best guesses are
1. That the memory map is as follows:
2. that for the DT's the following values should be used:
OPTEE_FRAMEBUFFER: = 0xDD000000 size 0x01000000 (in u-boot DT "optee-framebuffer)
DDR_SEC_BASE / SIZE = 0xDE000000 0x02000000 (in optee and uboot DT for "optee" and fw-config.dts firewall)
DDR_SHARED_BASE / SIZE = 0xDFE00000 0x00200000 (in fw-config firewall)
3. That the regions in the firewall in (in board-fw-config.dtsi) should be defined as follows:
//#define DDR_SEC_SIZE STM32MP_DDR_S_SIZE
//#define DDR_SEC_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE))
#define DDR_NS_SIZE (DDR_SEC_BASE - DDR_NS_BASE)
#define DDR_SHARE_SIZE 0x00200000
#define DDR_SEC_SIZE (STM32MP_DDR_S_SIZE - DDR_SHARE_SIZE)
#define DDR_SEC_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE - DDR_SHARE_SIZE))
#define DDR_SHARE_BASE (DDR_SEC_BASE + DDR_SEC_SIZE)
#ifdef AARCH32_SP_OPTEE
That is:
DDR_NS_BASE = 0xC0000000
DDR_NS_SIZE = 0x1E000000
DDR_SHARE_SIZE 0x00200000
DDR_SEC_SIZE 0x01A00000
DDR_SEC_BASE = 0xDE000000
DDR_SHARE_BASE = 0xDFE00000
memory-ranges = <
DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR
DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0
// PATCH Added for firewall shared memory 2MB area below top of DDR
DDR_SHARE_BASE DDR_SHARE_SIZE TZC_REGION_S_NONE TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID)
>;
#else
Conclusion, still the same error:
U-Boot 2022.10-stm32mp-r1 (Sep 21 2023 - 11:44:11 +0800)
CPU: STM32MP157AAA Rev.B
Model: STMicroelectronics STM32MP157C eval daughter on eval mother
Board: stm32mp1 in trusted mode (st,stm32mp157c-ev1)
DRAM: 512 MiB
E/TC:0 tzc_it_handler:79 TZC permission failure
E/TC:0 dump_fail_filter:420 Permission violation on filter 0
E/TC:0 dump_fail_filter:425 DEBUG: status = 0x1
E/TC:0 dump_fail_filter:426 DEBUG: IT_STATUS = 0x10
E/TC:0 dump_fail_filter:427 DEBUG: filter = 0x0
E/TC:0 dump_fail_filter:428 DEBUG: tzc.base = 0x34806000
E/TC:0 dump_fail_filter:429 DEBUG: FAIL_ID(filter) = 0x2c
E/TC:0 dump_fail_filter:431 Violation @0xdfb19000, non-secure privileged write, AXI ID 480
E/TC:0 Panic
fdtdump board.fw-config.dtb :
/ {
dtb-registry {
compatible = "fconf,dyn_cfg-dtb_registry";
hw-config {
load-address = <0x00000000 0xc0500000>;
max-size = <0x00040000>;
id = <0x00000002>;
};
nt_fw {
load-address = <0x00000000 0xc0100000>;
max-size = <0x00400000>;
id = <0x00000005>;
};
tos_fw {
load-address = <0x00000000 0x2ffc0000>;
max-size = <0x00022000>;
id = <0x00000004>;
};
};
st-mem-firewall {
compatible = "st,mem-firewall";
memory-ranges = <0xc0000000 0x1e000000 0x00000000 0x87fb87fb 0xde000000 0x01e00000 0x00000003 0x00000000 0xdfe00000 0x00200000 0x00000000 0x00010001>;
};
Attached the build log.
Funny footnote watching the STM32MP1 training video ... "This OPTEE , but can't remember what it does"... hm, so how I am supposed to learn this ? https://academy.st.com/s/learning-activity-detail-standard?ltui__urlRecordId=a5x3W000000ZXiBQAW<ui__urlRedirect=learning-activity-detail-standard<ui__parentUrl=learning-plan-detail-standard
