We are using timer peripheral in STM32MP157 Cortex -A7 core 0 processor. In this, we enabled TIM2, TIM3, TIM4 in RCC APB1 peripheral enable for MPU set register, now we unable to use these timers (not getting interrupts) in Cortex -A7 core 0 processor. But we enabled these same timers in RCC APB1 peripheral enable for MCU set register, at this time getting interrupts in Cortex -A7 core 0 processor.
So, any reason these timers (TIM2, TIM3, TIM4) enables in MCU set register to use in Cortex -A7 core 0 processor. remaining all peripherals are works with enables same MPU set register.
Maybe related to low power mode of Cortex-A7 and value in RCC_MP_APB1LPENSETR.
TIMers on APB1 need AHB2 clock running to generate interrupts, which might be forced to be enabled when you use MCU register if Cortex-M4 is not in low power mode.
See also Reference Manual "Peripheral clock gating control" and "Bus matrix and bridges clock gating" sections.