Wrong min. sample time mentioned in the STM32L475 data sheet.

[Harish1]

The min sample time is 2.5 ADC clock cycles and max.ADC clock is 80MHz, with this the sampling time is coming as 31.25ns but you mentioned as 18.75ns. Here, I think ST has taken the ADC clock cycles are 1.5. I felt it as a bug.

[Imen GH · Accepted solution]

Hello @Community member​ ,

Thanks for reporting this Typo

The sentence is wrong, and it should be corrected as follow:

“Down to 31.25ns sampling time�? Or “Down to 187.5 ns conversion time�?

Imen 

[Imen GH]

Hello,

I have raised internally the DS typo for fix in next release.

Thanks again.

Imen