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When the MCU is powered on or off, the GPIO will output a pulse at that moment.

Haixiang
Associate II

Greetings,

During the power-on and power-off processes of the STM32F407 chip, the GPIO used as the DAC output will be pulled high for 8ms. The goal is that the GPIO should remain low when there is no DAC output. Adding an external pull-down resistor has an effect but cannot completely eliminate it. It was not present during online debugging, only occurring when there was a power surge. After erasing the program, it still existed. Preliminary judgment is that it is a hardware issue. Is there any way to solve this problem?

Thank you so much for the help. @KDJEM.1 @LPetr.1 @TDK

 

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Haixiang_0-1749094234422.png

 

 

 

 

29 REPLIES 29
TDK
Super User

@waclawek.jan 

Nevermind. I do see a pulse on PA4 at power-on, but it disappears when a 1 kOhm pulldown is added. The pulse on PA4 at startup is somewhat higher than on other pins. Your reasoning here is likely correct.

Floating PA4:

IMG_4422.jpeg

With 1kOhm pulldown:

IMG_4424.jpeg

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Yes, it seems that VREF will exceed VDD. Because VREF is derived from 5V, and VDD is derived from 3V3. And 3V3 is obtained by reducing 5V.

Haixiang_0-1749516497746.png

 

At that time, I also tried a 1K pull-down, but it couldn't be completely eliminated. Could you describe the circuit you replicated? I didn't understand.

Perhaps it is because of the two 100μ capacitors in 3V3D that it fails to synchronize with the VREF voltage obtained from 5V during the power-up/down process. When powered on, the rise of VDD is slower than that of VREF, and when powered off, the drop of VDD is also slower than that of VREF.

I used a Nucleo board which has VDDA/VREF+/VDD all tied, so not quite the same circuit. I thought the behavior was the same but it was not.

Yes, in your circuit it's almost certainly due to VREF+ and VDDA not tracking each other.

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OK, I understand. Thank you again for your help.

waclawek.jan
Super User

I could quite well imagine also that the exact effect is dependent on exact threshold voltages of transistors, individual to every mcu, due to process variation. It may also depend on things like RC constants of the voltage rails, where R is ohmic resistance (and to certain extent inductance) of internal tracks and C is the sum of all parasitics loading these tracks internally. Besides transistors between the various voltage rails, there are also various protection and parasitic diodes, too. These all can interact during power-up/down in various surprising ways...

@TDK, please check my estimates: assuming the PA4 track at the Nucleo together with the scope probe's parasitic is around 100pF, the 100us rise time indicates cca 1MOhm "source", and the 1ms fall time indicates the 10MOhm impedance of a 1:10 probe. Even if this "calculation" would be one order of magnitude off, it's certainly not some "fully open" transistor to power rails; and as you've demonstrated, it should be quite possible to suppress it, if it is detrimental to the application... once one is aware of the existence of this effect, that is... However, the DAC's are also high output impedance (and the buffer is not rail-to-rail), so one may be hesitant to load it, so there some other means to mitigate this effect may be necessary (e.g. an external circuit pulling the output down while NRST is active).

JW

 

I didn't understand which transistor you were referring to. Is it in the 5V -> VREF circuit? Is it inside the MCU?

If it is in the 5V -> VREF circuit, then its threshold should not affect the result, right? Because its threshold value has little relation to the power-up and power-down speeds of VREF and VDD(The conduction time of the transistor? It should be done soon.). I think the main reason that causes these differences is the two 100μf capacitors connected by the VDD(Charging and discharging time).

If it is an internal circuit of the MCU, then I'm not quite sure.

> I didn't understand which transistor you were referring to

Inside the MCU. And I was only speculating. Sorry for the confusion.

JW

well.I'm not familiar with the internal circuits of the MCU.

Communicating with you has given me a lot of gains.Thanks.