When the MCU is powered on or off, the GPIO will output a pulse at that moment.

[Haixiang]

Greetings,

During the power-on and power-off processes of the STM32F407 chip, the GPIO used as the DAC output will be pulled high for 8ms. The goal is that the GPIO should remain low when there is no DAC output. Adding an external pull-down resistor has an effect but cannot completely eliminate it. It was not present during online debugging, only occurring when there was a power surge. After erasing the program, it still existed. Preliminary judgment is that it is a hardware issue. Is there any way to solve this problem?

Thank you so much for the help. @KDJEM.1 @LPetr.1 @TDK

[waclawek.jan]

> It seems that the VDDA and VSSA chips are not available.

I don't understand what do you mean by that.

How are these pins connected?

JW

[Haixiang]

VDDA is connected to VDD, and VSSA is connected to GND.

[Haixiang]

[waclawek.jan · Accepted solution]

1. Does the problem happen when you use the reset pushbutton?

2. As an experiment, try disconnecting TL431 from VREF+ and connecting VREF+ temporarily to VDD

3. What if the root of problem is some sort of current injection through the opamp connected to the DAC output, during the opamp's powerup? Try disconnecting the DAC output from the opamp (or removing the opamp itself, whichever is easier) and observe the DAC output alone. Or, alternatively, try to keep the opamp powered up, while powering down and then back up the mcu alone (having some means to disconnect the +5V rail, perhaps).

JW

[Haixiang]

1.This phenomenon occurs when the power is turned on and off. The reset button was not pressed.

2.I will attempt to observe the effect of connecting VREF to VDD.

3.Even without the operational amplifier chip, the same problem persists. We have already tried that.

[Haixiang]

Hello. Thank you for your help.After connecting VREF to VDD, everything worked fine. But I still don't understand why there was a problem here. Could you explain the reason?

[waclawek.jan]

Well, my guess is, that during the power-up, the following requirement is violated for a short period, due to the VREF+ rising slower than VDDA:

Or, it may be a similar problem, if VREF+ > VDDA briefly during powerup/powerdown.

JW

[TDK]

I duplicated this on power-on on the NUCLEO-F429ZI board on PA4 which has VREF+/VDDA tied. Could not see a pulse on power-off. Wonder what's different there.

[waclawek.jan]

@TDK,

Interesting.

Duplicated means that you see a pulse on PA4 at power-on? Were you able to measure its width and/or relationship with the VDDA rise, perhaps maybe also with VDD?

JW

[TDK]

@waclawek.jan Yes. Let me take another closer look later today. I'm surprised the fix was reported to work. It was something like a 1 V peak pulse with a ~50 ms decay time. That was with no external pulldown resistor.