What is the max voltage on a G0 pin configure as output?

[Konami]

It's not clear from the datasheet under what conditions pins are 5V tolerant, or what the pins can tolerate when configured as output. I'd like to know 2 things:

1. What is the max voltage on a pin (PB0) configured as open drain? I want to have it pulled up externally to 5V, and be able to pull low using the GPIO.
2. What is the max voltage on pins (PC6, PC7) configured as AF1 (TIM3_CH1/CH2). I want to use these with a 5V quadrature encoder without level shifting.

Does "Input voltage on FT_xx pins except FT_c" apply in these cases? If not, which limit does apply?

MCU: STM32G070CBT6

VDD: 3.3V

[Konami]

I did find this article, which helped clarify that my AF1 pins (PC6, PC7) are okay up to 5V. It also states that the pins are only 5V tolerant when configured as an input, which would seem to indicate that I'm violating the pin's max Vin in case 1. above. However, it still does not answer what the actual maximum voltage for a FT pin configured as output (push pull) is.

https://community.st.com/s/article/what-is-the-maximum-input-voltage-that-can-be-applied-to-my-stm32-gpio

[Tesla DeLorean]

Look at the IO Cell diagram, I'm pretty sure they only mean Push-Pull Output, and that the Open Drain, pull-up to 5V is the expected/anticipated use case, perhaps for I2C

[Konami]

I'm not familiar enough with the HW design to be confident, but I'll pass that on to an EE. I was thinking that too, but then I received a response to the contrary on my comment: https://community.st.com/s/article/what-is-the-maximum-input-voltage-that-can-be-applied-to-my-stm32-gpio

[gbm]

Slightly simplifying: when actively driving output to 1, it's shorted to Vdd. You don't want to short external 5 V to Vdd. You may safely pull the OD-configured output to 5 V via a resistor. In few of my projects I output the 1..2 MHz 5 V logic clock signal from STM32 using OD output with 1k5 pullup. It's not perfect but definitely usable.