VBAT current draw high just after VDD removed

[coppercrimp]

Posted on October 12, 2017 at 03:13

I have a custom circuit board with a STM32F407 part. Everything has worked fine with this board in past revisions, except on the most recent revision we increased the size of the output capacitor on the main regulator supplying power to the microcontroller. This caused an unexpected problem where the VBAT pin draws more current from the coincell backup battery when the main power is removed.

To quickly summarize, we have a BR1225 coincell connected to the VBAT pin to keep the RTC running when power is removed. The LDO supplying 3.3V to the board has a beefy 330uF capacitor on the output to reduce transient current spikes when the SD card (also on the board) is inserted or removed.

When the main power input is removed from the board, the 330uF capacitor can take some time to fully discharge to 0V. During the time the capacitor is discharging, the current draw on the VBAT pin is quite high. It does eventually settle down to 1uA once the output cap is completely discharged, but since the board is frequently turned on and off the coincell battery is depleted much faster than it was when we used a smaller output capacitor.

Has anyone else experienced this issue or have suggestions on how to fix it? I’ve considered adding some kind of auto discharge circuit to the board but wanted to explore other options before going down that road. Maybe I’m missing some setting with the Power Voltage Detector or brownout options.

Thanks in advance,

Rob

#vbat #stm32f4 #rtc-backup #high-currrent-draw-on-vbat Note: this post was migrated and contained many threaded conversations, some content may be missing.

[waclawek.jan]

Posted on January 18, 2018 at 21:32

I have VDDA connected to 3.3V power rail

I.e. it's directly connected the 330uF capacitor? Can you please measure it, directly touching the VDDA pin by the probe?

I'm not using the ADC or other analog features on my board

POR/brownout is tied to VDDA.

JW

[coppercrimp]

Posted on January 18, 2018 at 21:52

Yes VDDA is directly connected to the 330uF capacitor at the output of the linear regulator. My ohmmeter reads 0.2 ohms when measuring the resistance between the VDDA pin on the STM32 and positive side of the 330uF capacitor

[waclawek.jan]

Posted on January 18, 2018 at 22:11

Then I don't know... sorry.

JW

[T J]

Posted on January 18, 2018 at 23:51

Yes, A series resistor between the Coin Cell and the Processor pin.

please make sure you DO NOT have a bypass cap across the battery. It would be your problem if you had one.

a bypass cap would leak your battery flat in a week

[AVI-crak]

Posted on January 19, 2018 at 14:31

A real-time clock and a memory-protected area of memory are a very slow periphery, its speed is hundreds of kilohertz. For the possibility of recording and reading without long waiting, a buffer zone is used. The address is considered inaccessible at the time of long read / write, and gives / receives data at the end of the cycle on the slow side. In the interval between calls to the slow periphery, the system bus is able to perform other data transactions - to the faster peripherals.

This two directional node is turned on by the PWR_CR1_DBP command. When the main power starts to fall off, the logical unit voltage on the buffer management nodes on the backup memory side - parasitic power supply of the main power scheme. Because all field-effect transistors have a parasitic reverse diode. This continues until the kernel is reset. Repeated cycling of the main power supply may cause the clock to malfunction.

If you disable PWR_CR1_DBP recording during a voltage drop, then the spare area stores the data, there is no reverse current.

You can use the search in the IDE, to obtain data about PWR_CR1_DBP.

[José Pablo Crespo]

Posted on February 20, 2018 at 14:34

Hi Rob, did you leave unconnected PDR_ON, or tied to GND?

[coppercrimp]

Posted on February 20, 2018 at 18:47

Hi Jose, I'm using the STM32F407VGT chip. It's the LQFP100 pin package which does not have a PDR_ON pin. Thanks for your response though!

-Rob

[José Pablo Crespo]

Posted on February 21, 2018 at 09:57

Hello Rob, I think you might be able to fix it using some kind of power

supply supervisor circiut, enabling reset when Vdd drops, because when

resets are active, conmmunication between Vbat side and power side

stops. May be configuring the BOR in a different way. But I didn't use

407...

Good luck

Pablo Crespo

RE: VBAT CURRENT DRAW HIGH JUST AFTER VDD REMOVED

reply from Rob in STM32 MCUs Forum - View the full discussion