Using OnePulse mode with Repetition Counter on STM32G4 HRTIM

[DMcin.11]

I have an application which I prototyped on an STM32L476. It works fine, but I need to move up to an STM32G4 since I need extra processing power. I am driving the ADCs quite fast (5.35MHz) and need to use HRTIM to get the sampling times right (sampling the video output from an old TMS9928 chip...).

On the L476 I've been able to use several timers in OnePulse mode, and the one which clocks the ADCs is set up in OnePulse with RepetitionCounter=0xff. In this way I get a total of 256 samples per rising edge on the trigger input.

I've been trying to achieve the same on the G474, but with no success. I can get HRTIM1 to produce a single pulse in response to an edge on EEV1, but it ignores the repetition count. Is this supposed to work? If not, is there another way of achieving the result I'm looking for? I'm guessing either SYNC or Burst mode might work, but I've got to get my head around them, and I need to be sure they don't introduce any jitter.

And yes, I am using the HAL.

Any pointers gratefully appreciated. I've tried every combination of HAL_HRTIM_xxxStart I can think of to no avail. I just want to know if it's worth continuing to bang my head against this or if it's a waste of time.

Thanks

[MasterT]

ADC max. speed 4 MHz on G474, seems you need to configure two of them in dual mode interleaved. I don't understand why so precise sampling rate required, what happened if it would be 6 msps?

The problem with Timer's driven sampling, is that likely high jitter would happened, since ADC has it's own clock, and doesn't matter how precise external signal rising edge, ADC still would wait till it's own clock "clicks" - to initiate "sampling" phase. And I see that 170 MHz / 5.35 MHz has no integer divider.

Better approach is to run ADC with DMA on slightly higher rate, 170 / 31 = 5.48 , and set DMA to single short mode with required number of samples. CubeMX has examples on such project config.

[DMcin.11]

I should have known I wouldn't get away with that little information 🙂

You are correct on all counts, except that I'm cheating. The 9928 has a 10.7 MHz clock - hence the 535 MHz pixel time. I'm using the 10.7MHz to drive the MCO and end up overclocking the STM. I've got the STM32L476 running at FCLK=85.6 MHz, and the ADCs are sampling at 5.35MHz. Is use two ADCs runnin in syc dual mode, 6-bits, sampling the Y and R-Y outputs - that's enough data to recover the colours being generated since there are only 15 distinct level combinations. It works fine. I've actually tested it up to FCLK=96MHz and I'm sure it could go faster. My challenge is that I'm pushing data back out down SPI to a TFT and that baby is seriously overclocked. I'm amazed it works. Now I need more CPU time to be able to map the samples to the correct 16-bit levels for the TFT, so I need to move to e.g. the G4.

If I can run the ADC trigger from HRTIM I can place the sampling time in the middle of a pixel and the jitter won't matter too much. But I need to use HRTIM because I have to run FCLK at 18x the 10.7MHz in order to get a clock the TFT can handle. So there is no way of getting normal TIMs to produce ADC triggers at 5.35MHz.

So, back to my original question: is there in fact a way to make HRTIM actually use the repetition counter? Is it something to do with register preloading? There's nothing in the docs to say how to actually use is, and I can't find any examples.

Thanks,

D

[MasterT]

Have you seen: AN4539 Application note HRTIM cookbook

"3 Voltage mode dual buck converter

This section focuses on:

•repetition counter interrupts

•ADC trigger

•register update on repetition event.

Linked software:

https://github.com/STMicroelectronics/STM32CubeG4/tree/master/Projects/B-G474E-DPOW1/Examples_MIX/HRTIM/HRTIM_Dual_Buck

[Piranha]

For G4 with a basic timers (not HRTIM)...

SYSCLK = 10,7 * 31 / 2 = 165,85 MHz.

ADC sample rate = 165,85 / 31 = 5,35 MHz.

And with ADC trigger connected to the timer channel in compare mode, you have a 31 position for a phase delay, which can be adjusted even at runtime if necessary. Of course, one can replace the 31 with a higher factor in both equations to overclock the MCU.

[DMcin.11]

You mean 6-bit resolution so 6.5 cycles for conversion plus 24.5 cycles sampling?

I think that the DMA unit will want to insert an extra cycle when running in dual regular simultaneous mode, so that would make 32 cycles.

But even so, I need to have a clock for the SPI at just less than 50MHz for the TFT, otherwise I can't get the pixels out fast enough for each frame, so I have to run with an 18x clock multiplier.

But maybe I can use HRTIM to generate a clock for TIM1.....hmm

[DMcin.11]

It doesn't seem as if repetition means the same thing for an HRTIM as for a TIM. AFAICT in a TIM, the rep counter actually sets how many repetitions the counter will cycle through before stopping and waiting for another trigger, whereas in an HRTIM all it does is control how often to interrupt the CPU - every N repetitions. The counter doesn't seem to actually stop (in this example), it's just use to interrupt the CPU every 3 reps.

I still can't see why I'm only getting a single pulse though. I think repetition and single-shot mode don't mix.

[Piranha]

The trigger signal and ADC clock are two separate things. I looked at the datasheet - the ADC clock can be a maximum of 60 or 52 MHz for a single or multiple ADC instances running. In my example you can set PLLP=6 and feed a single ADC from that with 55,28(3) MHz. For multiple instances it would require changing the previously described factor of 31 to 29 and feed the ADC with 51,71(6) MHz.

And the only option to be able to get the 5,35 MHz sample rate is to set the sampling time to 2,5 ADC clock cycles and a resolution to 6-bit. The sampling time of 2,5 cycles also requires the channel to be the fast channel. Read the reference manual!