using Dual-Quad-SPI with OCTOSPI in STM32H5xx

[shii]

Hi,

I have been trying to connect PSRAM and NOR FLASH to STM32H563 nucleo board using Dual-Quad-SPI.

I was able to successfully read/write to PSRAM and NOR Flash individually in single-Quad-SPI mode with base address 0x90000000. i'm not clear how the addressing is taken care, when we connect both PSRAM and NOR Flash in dual-Quad-SPI mode.

[Nagarajan]

@KDJEM.1 

In first method, i am facing addressing problem for the second device in memory mapped mode.

I tried 2nd solution but i couldnt keep both NCS pins in the configuration. If I select second NCS pin, it is replacing with first one. Should i need to configure 2nd NCS pin as normal output pin and manually do the high or low for the second device?

[Tesla DeLorean]

Yes, I seriously doubt CubeMX/IDE is going to facilitates this at the auto-gen level, you'll have to take the training wheels off and code this behaviour yourself.

[Nagarajan]

Could you please explain the AF settings?

[KDJEM.1]

Hi @Nagarajan ,

--> In first method, i am facing addressing problem

Could you please give more details about the addressing issue?  To give more visibility by community members, I advise you to create a new thread about this issue.  

-->I tried 2nd solution but i couldnt keep both NCS pins in the configuration.

Which mode OCTOSPI are you using in STM32CubeMX?

With STM32CubeMx toolchain, you are able to configure only one memory. For that, I recommend you to code this behavior manually.

Thank you.

Kaouthar

[Nagarajan]

@KDJEM.1 @Tesla DeLorean 

is it fine to control NCS operation like below with normal GPIO output pin?

/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_RESET);
HAL_XSPI_Command(&hospi1, &cmd, HAL_MAX_DELAY);
HAL_XSPI_Receive(&hospi1, data, HAL_MAX_DELAY);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_SET);

[Tesla DeLorean]

AF - Alternate Function

Mux'd via GPIOx->AFR[x] / AFRL/AFRH

You're going to want to insure the NCS pin is PP or OD / PULLED-HIGH, and disconnect OCTOSPI1_NCS control from the pin/part you're NOT using.

Most of these H5 parts mention only OCTOSPI1

Just try to think through the need to not present signals to the unused device that would make it think it is connected, and that the clock/data is aimed at it, when it isn't.

[Tesla DeLorean]

I don't know, but using the HIGH / LOW data quads, ie D[7..4] and D[3..0] and a common clock / chip select for a RAM and NOR FLASH QSPI device is NOT going to work as desired.

Natively supporting this on the STM32H563ZITx with a single OCTOSPI doesn't seem particularly practical.

What would work is a singular (high or low) or dual pair of NOR FLASH, like W25Q512

[Nagarajan]

@KDJEM.1 @Tesla DeLorean 

I am able to switch the NCS functionality to other pins from PE11(NCS1) to PB10(NCS2) with manual coding but even though i choose ioselect as 0 to 3 or 4 to 7, the data is reflecting in other half. I chose single memory configuration only not dual quad configuration. Is this the expected behavior?

In this below pic you can see first data 06 (used HAL_XSPI_INSTRUCTION_1_LINE) i am sending to device A by making NCS pin low after that i am making NCS high (Deactivate device A and switching to Device B). Sending same data 06 to Device B by making NCS2 pin low. In this both the scenario you can see same data flowing through IO0 and IO4 but it is supposed to be go either IO0 or IO4. May i know the reason?

[Nagarajan]

Our real purpose of external ram and flash is if we dont have enough space from internal ram or flash, we will have to extend some part of code storage to flash similarly data for ram using linker script. We dont think this solution will work out for our problems. We feel like if microcontroller have two independent QUAD SPI peripherals, it will solve our problems. Is there any STM32 controllers having two independent QUAD-SPI peripherals?

[LCE]

The H72x / H73x have 2 independent OCTOSPI peripherals which also support QUAD SPI.

I'm currently working with STM32H735 Discovery Kit, with a (octal SPI) HyperRam and an octal SPI Flash, both working as they should.