Undocumented behavior of capture/compare registers

[rbraun]

Hello,

I tried to set a capture/compare register to a value beyond that of the auto-reload register, and the timer I used (TIM8) behaved as if the value had not been written. Reading back gives the expected value though. I haven't dug more but I'm curious : is there some undocumented behavior that prevents the shadow capture/compare register from having the value of the preload register if that value is higher than the auto-reload register ?

Please don't ask why I would do such a thing, that's just not the point.

Thanks.

[Tesla DeLorean]

It doesn't sanity check the content, they are just registers, there might be a comparator or equivalence signal, but I'm pretty sure it doesn't limit the setting, but rather drives an output used elsewhere in the TIM implementation

Some one would need to dig into the RTL to determine specific implementation detail.

@STOne-32  

[waclawek.jan]

What is the behaviour to expect, and how is the observed one different from it? 

JW

[BarryWhit]

?

[rbraun]

Right, my bad.

The expected behavior is to never have a compare event such as an interrupt, since the value of the counter can never become equal to that of the C/C register. What I observe is that I do get interrupts, and the value of the counter is barely above zero, which is the previous value of the C/C register, as if the new value was somewhat ignored.

[waclawek.jan · Accepted solution]

> The expected behavior is to never have a compare event such as an interrupt

That's an incorrect expectation.

JW

[rbraun]

Thank you very much.