Trigger from Timer does not trigger injected conversion on ADC

[Tobe]

JEOC nor JEOS triggers an interrupt. I already made sure that the ADC and the interrupt itself are working. (Regular conversion start by software).

Tried both trgo2 of timer and CC4 of timer to connect the adc with, which both did not work.

CCR4 is smaller than ARR.

I made sure that the registers were written like supposed. I did not find an issue:

STM32G431xx/ADC1/ISR:0x1
STM32G431xx/ADC1/ISR/JQOVF:0x0
STM32G431xx/ADC1/ISR/AWD3:0x0
STM32G431xx/ADC1/ISR/AWD2:0x0
STM32G431xx/ADC1/ISR/AWD1:0x0
STM32G431xx/ADC1/ISR/JEOS:0x0
STM32G431xx/ADC1/ISR/JEOC:0x0
STM32G431xx/ADC1/ISR/OVR:0x0
STM32G431xx/ADC1/ISR/EOS:0x0
STM32G431xx/ADC1/ISR/EOC:0x0
STM32G431xx/ADC1/ISR/EOSMP:0x0
STM32G431xx/ADC1/ISR/ADRDY:0x1
STM32G431xx/ADC1/IER:0x40
STM32G431xx/ADC1/IER/JQOVFIE:0x0
STM32G431xx/ADC1/IER/AWD3IE:0x0
STM32G431xx/ADC1/IER/AWD2IE:0x0
STM32G431xx/ADC1/IER/AWD1IE:0x0
STM32G431xx/ADC1/IER/JEOSIE:0x1
STM32G431xx/ADC1/IER/JEOCIE:0x0
STM32G431xx/ADC1/IER/OVRIE:0x0
STM32G431xx/ADC1/IER/EOSIE:0x0
STM32G431xx/ADC1/IER/EOCIE:0x0
STM32G431xx/ADC1/IER/EOSMPIE:0x0
STM32G431xx/ADC1/IER/ADRDYIE:0x0
STM32G431xx/ADC1/CR:0x10000001
STM32G431xx/ADC1/CR/ADCAL:0x0
STM32G431xx/ADC1/CR/ADCALDIF:0x0
STM32G431xx/ADC1/CR/DEEPPWD:0x0
STM32G431xx/ADC1/CR/ADVREGEN:0x1
STM32G431xx/ADC1/CR/JADSTP:0x0
STM32G431xx/ADC1/CR/ADSTP:0x0
STM32G431xx/ADC1/CR/JADSTART:0x0
STM32G431xx/ADC1/CR/ADSTART:0x0
STM32G431xx/ADC1/CR/ADDIS:0x0
STM32G431xx/ADC1/CR/ADEN:0x1
STM32G431xx/ADC1/CFGR:0x80000000
STM32G431xx/ADC1/CFGR/JQDIS:0x1
STM32G431xx/ADC1/CFGR/AWD1CH:0x0
STM32G431xx/ADC1/CFGR/JAUTO:0x0
STM32G431xx/ADC1/CFGR/JAWD1EN:0x0
STM32G431xx/ADC1/CFGR/AWD1EN:0x0
STM32G431xx/ADC1/CFGR/AWD1SGL:0x0
STM32G431xx/ADC1/CFGR/JQM:0x0
STM32G431xx/ADC1/CFGR/JDISCEN:0x0
STM32G431xx/ADC1/CFGR/DISCNUM:0x0
STM32G431xx/ADC1/CFGR/DISCEN:0x0
STM32G431xx/ADC1/CFGR/ALIGN:0x0
STM32G431xx/ADC1/CFGR/AUTDLY:0x0
STM32G431xx/ADC1/CFGR/CONT:0x0
STM32G431xx/ADC1/CFGR/OVRMOD:0x0
STM32G431xx/ADC1/CFGR/EXTEN:0x0
STM32G431xx/ADC1/CFGR/EXTSEL:0x0
STM32G431xx/ADC1/CFGR/RES:0x0
STM32G431xx/ADC1/CFGR/DMACFG:0x0
STM32G431xx/ADC1/CFGR/DMAEN:0x0
STM32G431xx/ADC1/CFGR2:0x0
STM32G431xx/ADC1/CFGR2/SMPTRIG:0x0
STM32G431xx/ADC1/CFGR2/BULB:0x0
STM32G431xx/ADC1/CFGR2/SWTRIG:0x0
STM32G431xx/ADC1/CFGR2/GCOMP:0x0
STM32G431xx/ADC1/CFGR2/ROVSM:0x0
STM32G431xx/ADC1/CFGR2/TROVS:0x0
STM32G431xx/ADC1/CFGR2/OVSS:0x0
STM32G431xx/ADC1/CFGR2/OVSR:0x0
STM32G431xx/ADC1/CFGR2/JOVSE:0x0
STM32G431xx/ADC1/CFGR2/ROVSE:0x0
STM32G431xx/ADC1/SMPR1:0x0
STM32G431xx/ADC1/SMPR1/SMP9:0x0
STM32G431xx/ADC1/SMPR1/SMP8:0x0
STM32G431xx/ADC1/SMPR1/SMP7:0x0
STM32G431xx/ADC1/SMPR1/SMP6:0x0
STM32G431xx/ADC1/SMPR1/SMP5:0x0
STM32G431xx/ADC1/SMPR1/SMP4:0x0
STM32G431xx/ADC1/SMPR1/SMP3:0x0
STM32G431xx/ADC1/SMPR1/SMP2:0x0
STM32G431xx/ADC1/SMPR1/SMP1:0x0
STM32G431xx/ADC1/SMPR1/SMPPLUS:0x0
STM32G431xx/ADC1/SMPR1/SMP0:0x0
STM32G431xx/ADC1/SMPR2:0x0
STM32G431xx/ADC1/SMPR2/SMP18:0x0
STM32G431xx/ADC1/SMPR2/SMP17:0x0
STM32G431xx/ADC1/SMPR2/SMP16:0x0
STM32G431xx/ADC1/SMPR2/SMP15:0x0
STM32G431xx/ADC1/SMPR2/SMP14:0x0
STM32G431xx/ADC1/SMPR2/SMP13:0x0
STM32G431xx/ADC1/SMPR2/SMP12:0x0
STM32G431xx/ADC1/SMPR2/SMP11:0x0
STM32G431xx/ADC1/SMPR2/SMP10:0x0
STM32G431xx/ADC1/TR1:0xfff0000
STM32G431xx/ADC1/TR1/HT1:0xfff
STM32G431xx/ADC1/TR1/AWDFILT:0x0
STM32G431xx/ADC1/TR1/LT1:0x0
STM32G431xx/ADC1/TR2:0xff0000
STM32G431xx/ADC1/TR2/HT2:0xff
STM32G431xx/ADC1/TR2/LT2:0x0
STM32G431xx/ADC1/TR3:0xff0000
STM32G431xx/ADC1/TR3/HT3:0xff
STM32G431xx/ADC1/TR3/LT3:0x0
STM32G431xx/ADC1/SQR1:0x0
STM32G431xx/ADC1/SQR1/SQ4:0x0
STM32G431xx/ADC1/SQR1/SQ3:0x0
STM32G431xx/ADC1/SQR1/SQ2:0x0
STM32G431xx/ADC1/SQR1/SQ1:0x0
STM32G431xx/ADC1/SQR1/L:0x0
STM32G431xx/ADC1/SQR2:0x0
STM32G431xx/ADC1/SQR2/SQ9:0x0
STM32G431xx/ADC1/SQR2/SQ8:0x0
STM32G431xx/ADC1/SQR2/SQ7:0x0
STM32G431xx/ADC1/SQR2/SQ6:0x0
STM32G431xx/ADC1/SQR2/SQ5:0x0
STM32G431xx/ADC1/SQR3:0x0
STM32G431xx/ADC1/SQR3/SQ14:0x0
STM32G431xx/ADC1/SQR3/SQ13:0x0
STM32G431xx/ADC1/SQR3/SQ12:0x0
STM32G431xx/ADC1/SQR3/SQ11:0x0
STM32G431xx/ADC1/SQR3/SQ10:0x0
STM32G431xx/ADC1/SQR4:0x0
STM32G431xx/ADC1/SQR4/SQ16:0x0
STM32G431xx/ADC1/SQR4/SQ15:0x0
STM32G431xx/ADC1/DR:0x0
STM32G431xx/ADC1/DR/RDATA:0x0
STM32G431xx/ADC1/JSQR:0x6a8
STM32G431xx/ADC1/JSQR/JSQ4:0x0
STM32G431xx/ADC1/JSQR/JSQ3:0x0
STM32G431xx/ADC1/JSQR/JSQ2:0x0
STM32G431xx/ADC1/JSQR/JSQ1:0x3
STM32G431xx/ADC1/JSQR/JEXTEN:0x1
STM32G431xx/ADC1/JSQR/JEXTSEL:0xa
STM32G431xx/ADC1/JSQR/JL:0x0
STM32G431xx/ADC1/OFR1:0x0
STM32G431xx/ADC1/OFR1/OFFSET1_EN:0x0
STM32G431xx/ADC1/OFR1/OFFSET1_CH:0x0
STM32G431xx/ADC1/OFR1/SATEN:0x0
STM32G431xx/ADC1/OFR1/OFFSETPOS:0x0
STM32G431xx/ADC1/OFR1/OFFSET1:0x0
STM32G431xx/ADC1/OFR2:0x0
STM32G431xx/ADC1/OFR2/OFFSET1_EN:0x0
STM32G431xx/ADC1/OFR2/OFFSET1_CH:0x0
STM32G431xx/ADC1/OFR2/SATEN:0x0
STM32G431xx/ADC1/OFR2/OFFSETPOS:0x0
STM32G431xx/ADC1/OFR2/OFFSET1:0x0
STM32G431xx/ADC1/OFR3:0x0
STM32G431xx/ADC1/OFR3/OFFSET1_EN:0x0
STM32G431xx/ADC1/OFR3/OFFSET1_CH:0x0
STM32G431xx/ADC1/OFR3/SATEN:0x0
STM32G431xx/ADC1/OFR3/OFFSETPOS:0x0
STM32G431xx/ADC1/OFR3/OFFSET1:0x0
STM32G431xx/ADC1/OFR4:0x0
STM32G431xx/ADC1/OFR4/OFFSET1_EN:0x0
STM32G431xx/ADC1/OFR4/OFFSET1_CH:0x0
STM32G431xx/ADC1/OFR4/SATEN:0x0
STM32G431xx/ADC1/OFR4/OFFSETPOS:0x0
STM32G431xx/ADC1/OFR4/OFFSET1:0x0
STM32G431xx/ADC1/JDR1:0x0
STM32G431xx/ADC1/JDR1/JDATA1:0x0
STM32G431xx/ADC1/JDR2:0x0
STM32G431xx/ADC1/JDR2/JDATA2:0x0
STM32G431xx/ADC1/JDR3:0x0
STM32G431xx/ADC1/JDR3/JDATA3:0x0
STM32G431xx/ADC1/JDR4:0x0
STM32G431xx/ADC1/JDR4/JDATA4:0x0
STM32G431xx/ADC1/AWD2CR:0x0
STM32G431xx/ADC1/AWD2CR/AWD2CH:0x0
STM32G431xx/ADC1/AWD3CR:0x0
STM32G431xx/ADC1/AWD3CR/AWD3CH:0x0
STM32G431xx/ADC1/DIFSEL:0x0
STM32G431xx/ADC1/DIFSEL/DIFSEL_0:0x0
STM32G431xx/ADC1/DIFSEL/DIFSEL_1_18:0x0
STM32G431xx/ADC1/CALFACT:0x4b
STM32G431xx/ADC1/CALFACT/CALFACT_D:0x0
STM32G431xx/ADC1/CALFACT/CALFACT_S:0x4b
STM32G431xx/ADC1/GCOMP:0x0
STM32G431xx/ADC1/GCOMP/GCOMPCOEFF:0x0

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STM32G431xx/TIM8/CR1:0xd1
STM32G431xx/TIM8/CR1/DITHEN:0x0
STM32G431xx/TIM8/CR1/UIFREMAP:0x0
STM32G431xx/TIM8/CR1/CKD:0x0
STM32G431xx/TIM8/CR1/ARPE:0x1
STM32G431xx/TIM8/CR1/CMS:0x2
STM32G431xx/TIM8/CR1/DIR:0x1
STM32G431xx/TIM8/CR1/OPM:0x0
STM32G431xx/TIM8/CR1/URS:0x0
STM32G431xx/TIM8/CR1/UDIS:0x0
STM32G431xx/TIM8/CR1/CEN:0x1
STM32G431xx/TIM8/CR2:0xc00005
STM32G431xx/TIM8/CR2/MMS_3:0x0
STM32G431xx/TIM8/CR2/MMS2:0xc
STM32G431xx/TIM8/CR2/OIS6:0x0
STM32G431xx/TIM8/CR2/OIS5:0x0
STM32G431xx/TIM8/CR2/OIS4N:0x0
STM32G431xx/TIM8/CR2/OIS4:0x0
STM32G431xx/TIM8/CR2/OIS3N:0x0
STM32G431xx/TIM8/CR2/OIS3:0x0
STM32G431xx/TIM8/CR2/OIS2N:0x0
STM32G431xx/TIM8/CR2/OIS2:0x0
STM32G431xx/TIM8/CR2/OIS1N:0x0
STM32G431xx/TIM8/CR2/OIS1:0x0
STM32G431xx/TIM8/CR2/TI1S:0x0
STM32G431xx/TIM8/CR2/MMS:0x0
STM32G431xx/TIM8/CR2/CCDS:0x0
STM32G431xx/TIM8/CR2/CCUS:0x1
STM32G431xx/TIM8/CR2/CCPC:0x1
STM32G431xx/TIM8/SMCR:0x0
STM32G431xx/TIM8/SMCR/SMSPS:0x0
STM32G431xx/TIM8/SMCR/SMSPE:0x0
STM32G431xx/TIM8/SMCR/TS_4_3:0x0
STM32G431xx/TIM8/SMCR/SMS_3:0x0
STM32G431xx/TIM8/SMCR/ETP:0x0
STM32G431xx/TIM8/SMCR/ECE:0x0
STM32G431xx/TIM8/SMCR/ETPS:0x0
STM32G431xx/TIM8/SMCR/ETF:0x0
STM32G431xx/TIM8/SMCR/MSM:0x0
STM32G431xx/TIM8/SMCR/TS:0x0
STM32G431xx/TIM8/SMCR/OCCS:0x0
STM32G431xx/TIM8/SMCR/SMS:0x0
STM32G431xx/TIM8/DIER:0x20
STM32G431xx/TIM8/DIER/TERRIE:0x0
STM32G431xx/TIM8/DIER/IERRIE:0x0
STM32G431xx/TIM8/DIER/DIRIE:0x0
STM32G431xx/TIM8/DIER/IDXIE:0x0
STM32G431xx/TIM8/DIER/TDE:0x0
STM32G431xx/TIM8/DIER/COMDE:0x0
STM32G431xx/TIM8/DIER/CC4DE:0x0
STM32G431xx/TIM8/DIER/CC3DE:0x0
STM32G431xx/TIM8/DIER/CC2DE:0x0
STM32G431xx/TIM8/DIER/CC1DE:0x0
STM32G431xx/TIM8/DIER/UDE:0x0
STM32G431xx/TIM8/DIER/TIE:0x0
STM32G431xx/TIM8/DIER/CC4IE:0x0
STM32G431xx/TIM8/DIER/CC3IE:0x0
STM32G431xx/TIM8/DIER/CC2IE:0x0
STM32G431xx/TIM8/DIER/CC1IE:0x0
STM32G431xx/TIM8/DIER/UIE:0x0
STM32G431xx/TIM8/DIER/BIE:0x0
STM32G431xx/TIM8/DIER/COMIE:0x1
STM32G431xx/TIM8/SR:0x3003f
STM32G431xx/TIM8/SR/TERRF:0x0
STM32G431xx/TIM8/SR/IERRF:0x0
STM32G431xx/TIM8/SR/DIRF:0x0
STM32G431xx/TIM8/SR/IDXF:0x0
STM32G431xx/TIM8/SR/CC6IF:0x1
STM32G431xx/TIM8/SR/CC5IF:0x1
STM32G431xx/TIM8/SR/SBIF:0x0
STM32G431xx/TIM8/SR/CC4OF:0x0
STM32G431xx/TIM8/SR/CC3OF:0x0
STM32G431xx/TIM8/SR/CC2OF:0x0
STM32G431xx/TIM8/SR/CC1OF:0x0
STM32G431xx/TIM8/SR/B2IF:0x0
STM32G431xx/TIM8/SR/BIF:0x0
STM32G431xx/TIM8/SR/TIF:0x0
STM32G431xx/TIM8/SR/COMIF:0x1
STM32G431xx/TIM8/SR/CC4IF:0x1
STM32G431xx/TIM8/SR/CC3IF:0x1
STM32G431xx/TIM8/SR/CC2IF:0x1
STM32G431xx/TIM8/SR/CC1IF:0x1
STM32G431xx/TIM8/SR/UIF:0x1
STM32G431xx/TIM8/EGR:null
STM32G431xx/TIM8/EGR/B2G:null
STM32G431xx/TIM8/EGR/BG:null
STM32G431xx/TIM8/EGR/TG:null
STM32G431xx/TIM8/EGR/COMG:null
STM32G431xx/TIM8/EGR/CC4G:null
STM32G431xx/TIM8/EGR/CC3G:null
STM32G431xx/TIM8/EGR/CC2G:null
STM32G431xx/TIM8/EGR/CC1G:null
STM32G431xx/TIM8/EGR/UG:null
STM32G431xx/TIM8/CCMR1_Output:0x5848
STM32G431xx/TIM8/CCMR1_Output/OC2M_3:0x0
STM32G431xx/TIM8/CCMR1_Output/OC1M_3:0x0
STM32G431xx/TIM8/CCMR1_Output/OC2CE:0x0
STM32G431xx/TIM8/CCMR1_Output/OC2M:0x5
STM32G431xx/TIM8/CCMR1_Output/OC2PE:0x1
STM32G431xx/TIM8/CCMR1_Output/OC2FE:0x0
STM32G431xx/TIM8/CCMR1_Output/CC2S:0x0
STM32G431xx/TIM8/CCMR1_Output/OC1CE:0x0
STM32G431xx/TIM8/CCMR1_Output/OC1M:0x4
STM32G431xx/TIM8/CCMR1_Output/OC1PE:0x1
STM32G431xx/TIM8/CCMR1_Output/OC1FE:0x0
STM32G431xx/TIM8/CCMR1_Output/CC1S:0x0
STM32G431xx/TIM8/CCMR1_Input:0x5848
STM32G431xx/TIM8/CCMR1_Input/IC2F:0x5
STM32G431xx/TIM8/CCMR1_Input/IC2PSC:0x2
STM32G431xx/TIM8/CCMR1_Input/CC2S:0x0
STM32G431xx/TIM8/CCMR1_Input/IC1F:0x4
STM32G431xx/TIM8/CCMR1_Input/ICPCS:0x2
STM32G431xx/TIM8/CCMR1_Input/CC1S:0x0
STM32G431xx/TIM8/CCMR2_Output:0x6868
STM32G431xx/TIM8/CCMR2_Output/OC4M_3:0x0
STM32G431xx/TIM8/CCMR2_Output/OC3M_3:0x0
STM32G431xx/TIM8/CCMR2_Output/OC4CE:0x0
STM32G431xx/TIM8/CCMR2_Output/OC4M:0x6
STM32G431xx/TIM8/CCMR2_Output/OC4PE:0x1
STM32G431xx/TIM8/CCMR2_Output/OC4FE:0x0
STM32G431xx/TIM8/CCMR2_Output/CC4S:0x0
STM32G431xx/TIM8/CCMR2_Output/OC3CE:0x0
STM32G431xx/TIM8/CCMR2_Output/OC3M:0x6
STM32G431xx/TIM8/CCMR2_Output/OC3PE:0x1
STM32G431xx/TIM8/CCMR2_Output/OC3FE:0x0
STM32G431xx/TIM8/CCMR2_Output/CC3S:0x0
STM32G431xx/TIM8/CCMR2_Input:0x6868
STM32G431xx/TIM8/CCMR2_Input/IC4F:0x6
STM32G431xx/TIM8/CCMR2_Input/IC4PSC:0x2
STM32G431xx/TIM8/CCMR2_Input/CC4S:0x0
STM32G431xx/TIM8/CCMR2_Input/IC3F:0x6
STM32G431xx/TIM8/CCMR2_Input/IC3PSC:0x2
STM32G431xx/TIM8/CCMR2_Input/CC3S:0x0
STM32G431xx/TIM8/CCER:0x414
STM32G431xx/TIM8/CCER/CC6P:0x0
STM32G431xx/TIM8/CCER/CC6E:0x0
STM32G431xx/TIM8/CCER/CC5P:0x0
STM32G431xx/TIM8/CCER/CC5E:0x0
STM32G431xx/TIM8/CCER/CC4NP:0x0
STM32G431xx/TIM8/CCER/CC4NE:0x0
STM32G431xx/TIM8/CCER/CC4P:0x0
STM32G431xx/TIM8/CCER/CC4E:0x0
STM32G431xx/TIM8/CCER/CC3NP:0x0
STM32G431xx/TIM8/CCER/CC3NE:0x1
STM32G431xx/TIM8/CCER/CC3P:0x0
STM32G431xx/TIM8/CCER/CC3E:0x0
STM32G431xx/TIM8/CCER/CC2NP:0x0
STM32G431xx/TIM8/CCER/CC2NE:0x0
STM32G431xx/TIM8/CCER/CC2P:0x0
STM32G431xx/TIM8/CCER/CC2E:0x1
STM32G431xx/TIM8/CCER/CC1NP:0x0
STM32G431xx/TIM8/CCER/CC1NE:0x1
STM32G431xx/TIM8/CCER/CC1P:0x0
STM32G431xx/TIM8/CCER/CC1E:0x0
STM32G431xx/TIM8/CNT:0x3c
STM32G431xx/TIM8/CNT/UIFCPY:0x0
STM32G431xx/TIM8/CNT/CNT:0x3c
STM32G431xx/TIM8/PSC:0xc
STM32G431xx/TIM8/PSC/PSC:0xc
STM32G431xx/TIM8/ARR:0x64
STM32G431xx/TIM8/ARR/ARR:0x64
STM32G431xx/TIM8/RCR:0x0
STM32G431xx/TIM8/RCR/REP:0x0
STM32G431xx/TIM8/CCR1:0x1
STM32G431xx/TIM8/CCR1/CCR1:0x1
STM32G431xx/TIM8/CCR2:0x1
STM32G431xx/TIM8/CCR2/CCR2:0x1
STM32G431xx/TIM8/CCR3:0x1
STM32G431xx/TIM8/CCR3/CCR3:0x1
STM32G431xx/TIM8/CCR4:0x50
STM32G431xx/TIM8/CCR4/CCR4:0x50
STM32G431xx/TIM8/BDTR:0x8800
STM32G431xx/TIM8/BDTR/BK2ID:0x0
STM32G431xx/TIM8/BDTR/BKBID:0x0
STM32G431xx/TIM8/BDTR/BK2DSRM:0x0
STM32G431xx/TIM8/BDTR/BKDSRM:0x0
STM32G431xx/TIM8/BDTR/BK2P:0x0
STM32G431xx/TIM8/BDTR/BK2E:0x0
STM32G431xx/TIM8/BDTR/BK2F:0x0
STM32G431xx/TIM8/BDTR/BKF:0x0
STM32G431xx/TIM8/BDTR/MOE:0x1
STM32G431xx/TIM8/BDTR/AOE:0x0
STM32G431xx/TIM8/BDTR/BKP:0x0
STM32G431xx/TIM8/BDTR/BKE:0x0
STM32G431xx/TIM8/BDTR/OSSR:0x1
STM32G431xx/TIM8/BDTR/OSSI:0x0
STM32G431xx/TIM8/BDTR/LOCK:0x0
STM32G431xx/TIM8/BDTR/DTG:0x0
STM32G431xx/TIM8/CCR5:0x0
STM32G431xx/TIM8/CCR5/CCR5:0x0
STM32G431xx/TIM8/CCR5/GC5C1:0x0
STM32G431xx/TIM8/CCR5/GC5C2:0x0
STM32G431xx/TIM8/CCR5/GC5C3:0x0
STM32G431xx/TIM8/CCR6:0x0
STM32G431xx/TIM8/CCR6/CCR6:0x0
STM32G431xx/TIM8/CCMR3_Output:0x0
STM32G431xx/TIM8/CCMR3_Output/OC6M_bit3:0x0
STM32G431xx/TIM8/CCMR3_Output/OC5M_bit3:0x0
STM32G431xx/TIM8/CCMR3_Output/OC6CE:0x0
STM32G431xx/TIM8/CCMR3_Output/OC6M:0x0
STM32G431xx/TIM8/CCMR3_Output/OC6PE:0x0
STM32G431xx/TIM8/CCMR3_Output/OC6FE:0x0
STM32G431xx/TIM8/CCMR3_Output/OC5CE:0x0
STM32G431xx/TIM8/CCMR3_Output/OC5M:0x0
STM32G431xx/TIM8/CCMR3_Output/OC5PE:0x0
STM32G431xx/TIM8/CCMR3_Output/OC5FE:0x0
STM32G431xx/TIM8/DTR2:0x0
STM32G431xx/TIM8/DTR2/DTPE:0x0
STM32G431xx/TIM8/DTR2/DTAE:0x0
STM32G431xx/TIM8/DTR2/DTGF:0x0
STM32G431xx/TIM8/ECR:0x0
STM32G431xx/TIM8/ECR/IE:0x0
STM32G431xx/TIM8/ECR/IDIR:0x0
STM32G431xx/TIM8/ECR/IBLK:0x0
STM32G431xx/TIM8/ECR/FIDX:0x0
STM32G431xx/TIM8/ECR/IPOS:0x0
STM32G431xx/TIM8/ECR/PW:0x0
STM32G431xx/TIM8/ECR/PWPRSC:0x0
STM32G431xx/TIM8/TISEL:0x0
STM32G431xx/TIM8/TISEL/TI1SEL:0x0
STM32G431xx/TIM8/TISEL/TI2SEL:0x0
STM32G431xx/TIM8/TISEL/TI3SEL:0x0
STM32G431xx/TIM8/TISEL/TI4SEL:0x0
STM32G431xx/TIM8/AF1:0x0
STM32G431xx/TIM8/AF1/ETRSEL:0x0
STM32G431xx/TIM8/AF1/BKCMP4P:0x0
STM32G431xx/TIM8/AF1/BKCMP3P:0x0
STM32G431xx/TIM8/AF1/BKCMP2P:0x0
STM32G431xx/TIM8/AF1/BKCMP1P:0x0
STM32G431xx/TIM8/AF1/BKINP:0x0
STM32G431xx/TIM8/AF1/BKCMP7E:0x0
STM32G431xx/TIM8/AF1/BKCMP6E:0x0
STM32G431xx/TIM8/AF1/BKCMP5E:0x0
STM32G431xx/TIM8/AF1/BKCMP4E:0x0
STM32G431xx/TIM8/AF1/BKCMP3E:0x0
STM32G431xx/TIM8/AF1/BKCMP2E:0x0
STM32G431xx/TIM8/AF1/BKCMP1E:0x0
STM32G431xx/TIM8/AF1/BKINE:0x0
STM32G431xx/TIM8/AF2:0x0
STM32G431xx/TIM8/AF2/OCRSEL:0x0
STM32G431xx/TIM8/AF2/BK2CMP4P:0x0
STM32G431xx/TIM8/AF2/BK2CMP3P:0x0
STM32G431xx/TIM8/AF2/BK2CMP2P:0x0
STM32G431xx/TIM8/AF2/BK2CMP1P:0x0
STM32G431xx/TIM8/AF2/BK2INP:0x0
STM32G431xx/TIM8/AF2/BK2CMP7E:0x0
STM32G431xx/TIM8/AF2/BK2CMP6E:0x0
STM32G431xx/TIM8/AF2/BK2CMP5E:0x0
STM32G431xx/TIM8/AF2/BK2CMP4E:0x0
STM32G431xx/TIM8/AF2/BK2CMP3E:0x0
STM32G431xx/TIM8/AF2/BK2CMP2E:0x0
STM32G431xx/TIM8/AF2/BK2CMP1E:0x0
STM32G431xx/TIM8/AF2/BKINE:0x0
STM32G431xx/TIM8/DCR:0x0
STM32G431xx/TIM8/DCR/DBL:0x0
STM32G431xx/TIM8/DCR/DBA:0x0
STM32G431xx/TIM8/DMAR:0xc1
STM32G431xx/TIM8/DMAR/DMAB:0xc1

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Here is my ADC setup:

	//TODO: forbiddden write accesses nochmal prüfen! Kritisch! S. 614

	//__HAL_RCC_ADC12_CLK_ENABLE();	// Enable peripheral clock
	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN);
	delayMicroseconds(1);
	SET_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL_1);	//PLL clock?

	delayMicroseconds(1);			//CAUTION: 	Just after enabling the clock for a peripheral, software must wait for a delay before accessing the peripheral registers.

	ADC1->CR &= ~ADC_CR_DEEPPWD;	// Disable power down (is default after reset)

	ADC1->CR |= ADC_CR_ADVREGEN;	// Enable voltage regulator

	delayMicroseconds(25); 			// Wait for voltage regulator to start up (fixed value of datasheet!)

	ADC1->CR |=	ADC_CR_ADCAL;		// Calibrate single ended (ADCALDIF is default 0)

	while(ADC1->CR & ADC_CR_ADCAL);	// Wait until calibration has finished

	delayMicroseconds(1); 			// ADC can only be enabled after short wait after ADCAL

	ADC1->ISR |= ADC_ISR_ADRDY;		// Clear ready bit by writing 1, for reading the right status below

	ADC1->CR |=	ADC_CR_ADEN;		// Enable ADC

	while((ADC1->ISR & ADC_ISR_ADRDY) == false); 					// Wait until ready


	ADC1->JSQR |= (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1);	// JEXTSEL trigger select 01010 trgo2 adc_jext_trg10
	//ADC1->JSQR |= (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0);	// JEXTSEL trigger select 01010 trgo2 adc_jext_trg10

	ADC1->JSQR |= (ADC_JSQR_JSQ1_1 | ADC_JSQR_JSQ1_0);			// Channel 3 injected

	ADC1->IER |= ADC_IER_JEOSIE;								// Interrupt on end of conversion injected

	// TODO: oversampling möglich per hardware !!!!

	ADC12_COMMON->CCR |= (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0);		// Injected simultaneous mode DUAL mode ADC 1 + 2

	ADC1->JSQR |= ADC_JSQR_JEXTEN_0; 							// Enable injected External trigger

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This is the Timer setup:

__HAL_RCC_TIM8_CLK_ENABLE();		// Enable clock

	CLEAR_REG(TIM8->AF1);				// Disable BKIN input
	CLEAR_REG(TIM8->AF2);

	SET_BIT(TIM8->CR1, 	TIM_CR1_ARPE | 	// ARR register is bufferd
						TIM_CR1_CMS_1 	// center aligned up/down (interrupt on counting up - for ADC trigger only?)
						);

	//TODO: check entries again for pwm
	SET_BIT(TIM8->CR2, 	TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | // tim_oc4refc or tim_oc6refc rising edges generate pulses on	tim_trgo2 for ADC trigger
						TIM_CR2_CCPC |	// Preload enable
						TIM_CR2_CCUS);

	//TIMx_ARR -1 ist max counter (Counter is counted up and down, so PWM has half the tics)
	WRITE_REG(TIM8->ARR, PWM_HALF_CYCLE_TICS); 	// Counter TOP
	WRITE_REG(TIM8->CCR4, PWM_HALF_CYCLE_TICS - ADC_TRIG_PRE_COUNT);	// compare value 4 (ADC trigger)

	// Prescaler 12 for 34kHz
	TIM8->PSC = 12;

	//TODO: DEBUG REMOVE
	setDuty(1);
//	WRITE_REG(TIM8->CCR1, DUTY_TO_TICS(10));	// compare value 1
//	WRITE_REG(TIM8->CCR2, DUTY_TO_TICS(10));	// compare value 2
//	WRITE_REG(TIM8->CCR3, DUTY_TO_TICS(10));	// compare value 3

	SET_BIT(TIM8->CCMR1, 	TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1	| // pwm output compare polarity channel 1 and 2 (pwm mode 1)
							TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 |
							TIM_CCMR1_OC1PE  | TIM_CCMR1_OC2PE); 	// preload enable ccr 1 + 2
	// Default is OUTPUT !!!
	// CC1S = 0 > channel output (CC1 as OUTPUT)

	SET_BIT(TIM8->CCMR2, 	TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1	| // pwm output compare polarity channel 3 and 4 (pwm mode 1)
							TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1 |
							TIM_CCMR2_OC3PE  | TIM_CCMR2_OC4PE); 	// preload enable ccr 3 + 4


	// Timer 1 trigger out comes in on itr0 (Only trgo is possible!)
	//TIM8->SMCR itr0 is default 0!



	SET_BIT(TIM8->BDTR, TIM_BDTR_OSSR); // inactive state high or low
	CLEAR_BIT(TIM8->CCER, TIM_CCER_CC1P);// oc1 polarity active high
	CLEAR_BIT(TIM8->CCER, TIM_CCER_CC2P);// oc2 polarity active high
	CLEAR_BIT(TIM8->CCER, TIM_CCER_CC3P);// oc3 polarity active high

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[Tobe · Accepted solution]

Figured it out how it (should?) works:

ADC1->CR |= ADC_CR_JADSTART; // A start is needed, so the event trigger would work!

Havent found this information in the manual!