The speed of the stm32 GPIO (different series).

[Alexey Vergin]

Dear engineers. I want to read an extern parallel ADC directly connected to GPIO ports of stm32 microcontroller and clocked from it. It is necessary to make 1000 readings from the ADC with a maximum speed and write them to stm32 memory. What is the maximum access speed for ports for different stm32 series, which is more profitable, use DMA (CPUs and interrupts will be disabled for the duration of DMA operation) or reading by the assembler commands (all DMA channels and all interrupts will be disabled, without organizing aтн cycle).

[Alexey Vergin]

Thank you. Definitely for FPGA. But the controller has free pads. And I very want to try to use them.

>> maybe if it would turn out to be 2-cycle, I'd add an artificial NOP

Why is that? It would seem that the less the better

[berendi]

As long as there is a possibility that the ADC puts the data on the bus at the same time (clock edge) when the MCU reads it, data can be corrupted. It can depend on the data pattern, or environmental factors, you can never be sure. (set the wrong clock phase on parallel display adapters and observe results)

I'd get an STM32H7, and try to do something with the FMC, QSPI, or maybe MDMA + a high speed timer

BTW, according to AN4031 the dual port DMA controllers can do a copy in 3 AHB cycles. I couldn't find the MDMA timings, but connected to the AXI bus it might be faster, and might be triggered with a suitably offset timer output.

[Alexey Vergin]

>> As long as there is a possibility that the ADC puts the data on the bus at the same time (clock edge) when the MCU reads it, data can be corrupted. It can depend on the data pattern, or environmental factors, you can never be sure. (set the wrong clock phase on parallel display adapters and observe results)

not a problem. I can clock adc in one controller period, and read it in the other.

[Alexey Vergin]

>> I'd get an STM32H7, and try to do something with the FMC, QSPI, or maybe MDMA + a high speed timer

 >>BTW, according to AN4031 the dual port DMA controllers can do a copy in 3 AHB cycles. I couldn't find the MDMA timings, but connected to the AXI >>bus it might be faster, and might be triggered with a suitably offset timer output.

Thank you. I will watch

[berendi]

> I can clock adc in one controller period, and read it in the other.

That's exactly what I'm curious about. How?

[Alexey Vergin]

What's the problem? Tacting an ADC through a timer. I synchronize the assembler program with a timer so that I can read the ADC when the timer output is 0. At the same time, the previous measurement is guaranteed at the ADC output. And when the timer goes to 1, and the state of the ADC changes, we mess with the memory.

[waclawek.jan]

> BTW, according to AN4031 the dual port DMA controllers can do a copy in 3 AHB cycles.

No, it can't. Re-read AN4031, concentrate on chapter 3.1.1. Default DMA transfer timing. Note, that one transfer consists from transfer on Peripheral port + transfer on Memory port.

JW