The question of setting clock multipliers and dividers

[yang2]

Dear All,

I've been using MCU/DSP-related products for over 10+ years, but I've always had some confusion about clock multipliers and dividers. I'd like to ask for everyone's opinion on this topic.

As shown as below figure (it's the clock configuration of the STM32H563), if I want the SYSCLK clock signal to be 120MHz, I can configure it as follows: CSI is the source clock (4MHz), and along the way, it passes through a divider of /1, a multiplier of x60, and then a divider of /2, resulting in a final SYSCLK of 120MHz.

/1    x60    /2

But we can also achieve a SYSCLK of 120MHz through the following configurations of multipliers and dividers.

/ 4  x240   /2    =120MHz

/2    *240    /4   = 120MHz

So, which configuration would be better?

In my thinking, it seems like it's better to minimize the multiplier and divider values as much as possible, in order to maintain the clock source closer to its original. (This implies that case 1 is better than case 2 and case 3, as it uses the smallest multiplier and divider values.)

I'm not sure if this is the correct concept, so I'd like to ask for others' opinions.

Best Regards,

[Andrew Neil]

@STTwo-32  I think this would be a good topic for an Application Note and/or a Knowledge Base article!

[MasterT · Accepted solution]

The parameter you are hunting is called PLL / VCO jitter. Look in the data sheet, and on-line. Higher multiplier degrades specification, since VCO is running for longer period of time and drift away w/o syncing.

Jitter is more important for analog domain of the uCPU, for ADC & DAC.

I did some test on stm32G474re where I observed improvement in ADC performance sampling high frequency input signal when PLL configured for smallest N /M factors