Best PLL Multiply and Divider setting

[SJame.1]

Using the PLL generated system clock frequency, it is possible to generate the same output frequency with many different pre-divider, Multiplier and post divider constant combinations. How can I determine combination is best for stability or lowest power operation. I assume keeping the PLL osc output frequency as low as possible would keep the current consumption at a minimum. Any guidance or helpful tips /application notes. Using F0, G0, C0 and G4 series CPUs

[Tesla DeLorean]

Usually it comes down to the preferred comparison frequency range, and the most stable operating region of the VCO pulse generation.​

On the F2/F4 this was 1-2 MHz and 200-400 MHz.

Y​ou always need to divide the VCO down by a power of 2 to get 50/50 duty cycle square waves to clock the MCU

[SJame.1]

Ok, thanks Tesla, Just asked stm32CubeMX (V6.8) to do it and its given PLLM= div1, N=x9, /R=div3 for HSI16. on G031

[SJame.1]

for 48MHZ

[waclawek.jan]

For some families' PLL, there may be some preferential setting, e.g. for 'F4:

For 'G0, there may be no such stated preference, I did not search. In that case, any combination which obeys the limits for PLL's VCO and dividers, given in DS, will do.

Note, that PLL is to large extent analog and such preferences change from family to family because of different technologies and PLL component designs used, so such preferences are not transferrable.

PLL settings may also influence current consumption, within limits given for the PLL module.

 

JW

[Piranha]

A general note... With everything else being equal, one should strive to minimize the numeric values of all multipliers and dividers.