Synchronize peripherals SAI & I2S output clocks

[LCE]

Heyho,

I'm using a H733 with both SAI 1 and SAI 4 with SAI 1 as I2S clock master to get 8 synced audio channels.

Audio clock comes from I2SCKIN, this is used for SAIs and I2S.

Problem: because of the fixed oversampling ratio (256 or 512) of the SAI, I have to use an SPI/I2S peripheral to generate the "MCLK" to make 200 kHz possible, with 200 kHz x 128 = 25.6 MHz.

That's basically working, but I wonder why sometimes at start (not while running) the MCLK (from SPI/I2S) shifts by 180° / is inverted, in relation to the SAI/I2S clocks (SCLK (=SCK), LRCK (=WS)).

For regular audio stuff this is not a problem, but I have another slave on the I2S bus doing other things which needs a fixed phase relation between MCLK and LRCK / SCLK (previously controlled by an FPGA).

So how are theses clocks generated that this phase shift can happen, with the same clock input , and "going through" the same hardware each time?

What can I do to sync these clocks?

[waclawek.jan]

What is the MCLK divider, i.e. what is the I2SCKIN frequency?

If it's not 2*MCLK, I'd wonder, how comes, that the phase shift is only 180deg. I'd expect it to be all over the place. The only synchronization mechanism you have in place now is just expecting consistent execution timing between setting up/enabling the separate divider chains, isn't it. And given the incredibly complicated beasts 'H7 are, and the fact that you apparently run the I2S from a clock asynchronous to the processor clock, such synchronicity is far from being trivial to achieve.

You do disable all; interrupts during the I2S/SPI and SAI setup, don't you.

If yes, and you already run from some half-predictible code memory like ITCM, then IMO the only option is to generate the complete clocks mix using e.g. a timer, and feed that back into the SAIs being set up as slaves.

JW

PS. Yes, the fixed MCLK divider ratio is annoying.