Hi guys,
I'm "trying" to establish a STABLE communication between USB FX2LP sync slaveFIFO and STM32 MCU, in particular with the STM32L412KB for now.
I need a stable data transfer from STM32 DMA-GPIO to FX2LP slaveFIFO with DMA clock 3MHz (later higher on other MCUs).
I know this is not the smartest idea, I'd rather do it with FPGA, etc., but thanks to chip shortage, FPGAs have become a rare animal and quite expensive one. And I do believe it is possible to implement with timers, with quite precise timings.
I'm planning to use TIM1 which is triggered by rising edge of ETR (to which I connect MCO, so I have a stable delay between rising edge of MCO and trigger event/signal).
By the TRGO of TIM1 I'll start TIM2 and TIM15 with predefined params, though ITR0 to TRGI. I made a drawings, did several attempts and all of them were fail.
I'm not sure how to configure it and if possible at all, the way I have shown in on drawings.
Any help is much appreciated!
